Inclined Interconnect and Via Structure for Lower-Resistance Semiconductors
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Solution Overview
Problem
The increasing integration of semiconductor devices leads to challenges in reducing the resistance of interconnection layers and vias and increasing capacitance between them, which affects the electrical characteristics and reliability of the devices.
Innovation Solution
The semiconductor device incorporates a design with inclined side surfaces in interconnection layers and vias, using different metals for each layer, and is formed through specific etching processes to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of transistors and interconnection layers is reduced to increase integration, then device integration increases, but interconnection resistance increases and capacitance decreases
Solution Approach 1:
The patent changes the geometric parameters of interconnection structures by forming inclined side surfaces on interconnection layers and vias. This parameter change increases the effective contact area and improves electrical connectivity, thereby reducing resistance and enhancing capacitance without requiring larger physical dimensions, thus maintaining high integration while improving electrical characteristics
Solution Approach 2:
The patent employs composite material structures by forming multi-layered interconnection systems with different metals (e.g., copper, cobalt, tungsten) and combining them with insulating materials having specific dielectric properties. This composite approach optimizes both electrical performance (lower resistance, higher capacitance) and structural integrity in highly integrated devices
2Ease of manufacture
If conventional etching processes are used for via formation, then manufacturing is simpler, but interfacial damage and resistance increase
Solution Approach 1:
The patent applies preliminary actions by performing surface preparation steps before via formation, including forming protective layers and controlling etching conditions in advance. This preliminary preparation prevents interfacial damage during the etching process, reducing defects and improving reliability while maintaining manufacturing feasibility
Solution Approach 2:
The patent introduces intermediary protective layers and controlled etching processes that act as mediators between the etching tool and the interconnection structures. These intermediaries protect sensitive interfaces from damage while allowing the etching process to proceed, thereby reducing interfacial damage without significantly complicating manufacturing
Data Source
AI summary
A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.