Inclusive Cache Probe Filtering via Fetch Request Retention

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Solution Overview

Problem

Conventional cache hierarchies face challenges in effectively filtering probes due to the uncertainty caused by the possibility of fetch or prefetch requests being canceled by underlying caches, which limits the ability of higher-level caches to determine the residency of cache lines and maintain coherence.

Innovation Solution

Configuring underlying caches to prevent cancellation of fetch or prefetch requests issued to higher-level inclusive caches, using inclusion bits to indicate the presence of cache lines and allowing the higher-level cache to filter probes based on these bits, thereby reducing uncertainties and improving filtering efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If underlying caches are configured to prevent cancellation of fetch or prefetch requests, then the higher-level cache can effectively filter probes and reduce power consumption, but the flexibility of the cache system to handle speculative instructions is reduced

Engineering Contradiction:
Improvepower consumptionVSAvoidflexibility to handle speculative instructions
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent segments the cache system into multiple levels (L1, L2, L3 caches) with distinct responsibilities. The higher-level cache is segmented to handle probe filtering independently, while underlying caches maintain their request management. This segmentation allows the higher-level cache to effectively filter probes without requiring changes to the underlying caches' request cancellation capabilities, thus reducing power consumption while preserving flexibility at different cache levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The higher-level cache acts as an intermediary between external probe requests and underlying caches. By implementing probe filtering at this intermediate level, the system can block unnecessary probes before they reach lower-level caches, reducing overall power consumption. The intermediary maintains coherence by only allowing probes through when necessary, while underlying caches retain their ability to cancel requests for speculative instructions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If fetch or prefetch requests can be canceled by underlying caches, then the system can handle speculative instructions efficiently, but the higher-level cache cannot effectively filter probes due to uncertainty about cache line residency

Engineering Contradiction:
Improvefiltering efficiencyVSAvoiduncertainty about cache line residency
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by having the higher-level cache establish probe filtering capabilities before probe requests arrive. The higher-level cache pre-configures its filtering logic based on inclusion bits and cache state information, so that when probes arrive, it can immediately filter them without uncertainty. This preliminary preparation allows effective probe filtering even when underlying caches may cancel fetch requests, as the filtering decision is based on pre-established state information.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback mechanisms where the higher-level cache monitors the state of underlying caches through inclusion bits and cache coherence protocols. This feedback allows the higher-level cache to adjust its probe filtering decisions dynamically. When the higher-level cache receives feedback indicating that a cache line is present in an underlying cache (through inclusion bits or coherence signals), it can filter probes appropriately, maintaining filtering efficiency even when request cancellation is possible.

Inventive Principle:
Principle #23Feedback

3Loss of energy

If the higher-level cache filters probes based on inclusion bits, then power consumption is reduced, but the complexity of managing inclusion bits and probe filtering logic increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcomplexity of probe filtering logic
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the probe filtering logic with the existing cache coherence management infrastructure. The higher-level cache combines probe filtering with its existing functions of maintaining inclusion bits and managing cache coherence. By merging these functions, the system reduces power consumption through effective filtering without adding separate complex filtering hardware or logic. The unified approach leverages existing structures to achieve filtering efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The higher-level cache performs self-service by autonomously managing its own probe filtering based on its internal state information (inclusion bits). Rather than requiring external control or complex coordination with lower-level caches, the higher-level cache independently determines which probes to filter based on its cached state information. This self-service approach reduces power consumption through filtering while keeping the logic relatively simple, as each cache level makes independent filtering decisions based on local information.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9122612B2Eliminating fetch cancel for inclusive caches
Publication Date: 2015.09.01 ADVANCED MICRO DEVICES INC
  • US9122612B2 patent drawing
  • US9122612B2 patent drawing
  • US9122612B2 patent drawing

AI summary

A method and apparatus for eliminating fetch cancels for inclusive caches are presented. Some embodiments of the apparatus include a first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache. The first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. Some embodiments of the method include preventing the first cache(s) from canceling issued fetch or prefetch requests to a second cache that is inclusive of the first cache(s).