Incoherency Detection Module for Multi-Threaded Cache Coherence
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Solution Overview
Problem
In multi-threaded processors, data incoherency arises when multiple threads access shared global cache lines, leading to incorrect data retrieval due to the timing differences between read and write requests, particularly in write-through caches, causing threads to read old values.
Innovation Solution
An incoherency detection module is introduced to track previous global write requests and enforce order through a Global Write Address Memory (GWAM) and order enforcement sidebands, ensuring that read or write instructions are only issued when safe, preventing data incoherency by inserting barriers as necessary to maintain data coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write-through cache policy is used to ensure writes are visible to all threads, then write visibility is improved, but data incoherency occurs when reads happen before writes complete
Solution Approach 1:
The patent applies preliminary action by inserting barrier requests before write requests in the request queue. These barriers ensure that read requests wait until preceding write requests have been issued to the memory bus before being allowed to proceed. This prevents reads from occurring before writes are visible, eliminating data incoherency while maintaining write-through cache policy benefits.
2Speed
If read requests are allowed to proceed immediately without waiting for prior writes, then read performance is improved, but data incoherency arises due to timing differences
Solution Approach 1:
The patent implements feedback through the barrier mechanism that monitors the state of write requests. When a read request arrives, the system checks whether preceding write requests have been issued to the memory bus. Based on this feedback, the read request is either allowed to proceed immediately (if writes are already issued) or is blocked until writes complete. This maintains data coherence while minimizing read wait time.
3Reliability
If barriers are inserted for every read request to ensure data coherence, then data coherence is improved, but data flow is stalled and performance deteriorates
Solution Approach 1:
The patent applies partial action by inserting barriers only when necessary - specifically when a read request follows a write request that has not yet been issued to the memory bus. Barriers are not inserted for every read request, but only when the timing conditions create a potential incoherency hazard. This selective barrier insertion maintains data coherence while minimizing impact on data flow throughput.
Data Source
AI summary
A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.