Incomplete Super Block Reconfiguration for Flash Write Performance

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Solution Overview

Problem

Memory systems face reduced write performance due to the accumulation of defective blocks, leading to incomplete super blocks and unused capacity, as they cannot maintain full parallelism and efficient data migration from SLC to TLC mode, resulting in increased programming time and decreased endurance.

Innovation Solution

The system reconfigures incomplete super blocks into complete ones by reassigned orphan blocks within planes, allowing for maximum parallel operations and writing data in SLC mode to complete super blocks before migrating to TLC mode, thereby enhancing write performance and reducing unused capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the system uses traditional super block management ignoring defective blocks, then the structure remains simple, but write performance decreases due to incomplete super blocks and loss of parallelism

Engineering Contradiction:
Improvewrite performanceVSAvoidsuper block management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic super block management where the system continuously monitors block status and reconfigures super blocks in real-time. When defective blocks are detected, the system dynamically adjusts super block compositions by replacing defective blocks with spare blocks, ensuring complete super blocks are always available for parallel write operations. This dynamic adaptation maintains high write performance without requiring complex static reconfiguration schemes.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of super block composition by maintaining multiple possible configurations. It tracks the status of all blocks and maintains a pool of spare blocks that can be substituted into super blocks as needed. This parameter change approach allows the system to transform incomplete super blocks into complete ones, maximizing parallelism and write performance while managing complexity through systematic parameter tracking.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the system allocates spare capacity to replace defective blocks, then reliability improves, but the loss of substance (unused capacity) increases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidunused memory capacity
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent implements a block recovery mechanism where defective blocks are identified and removed from active super blocks, then replaced with spare blocks from the unused capacity pool. This allows the system to recover functionality from defective blocks while systematically managing the spare capacity. The recovered blocks can be repurposed or added to the spare pool, minimizing permanent loss of substance while maintaining reliability.

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 2:

The system converts the harmful effect of defective blocks into a benefit by using them as indicators to trigger reconfiguration. When defective blocks are detected, the system automatically initiates super block reconfiguration, which can improve overall system reliability by distributing data across healthier blocks. The presence of defective blocks thus benefits the system by prompting proactive management actions that prevent future failures and optimize capacity utilization.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Speed

If the system maintains complete super blocks for parallel operations, then write speed increases, but the difficulty of detecting and measuring defective blocks increases

Engineering Contradiction:
Improvewrite speedVSAvoiddefective block detection complexity
Core Design Contradiction:
SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously monitors write operations and block status. When a defective block is detected during write operations or through periodic scanning, the feedback triggers automatic super block reconfiguration. This feedback loop ensures that complete super blocks are maintained for parallel operations while systematically detecting and responding to defective blocks, balancing write speed requirements with detection complexity through automated responses.

Inventive Principle:
Principle #23Feedback

4Productivity

If the system performs frequent super block reconfiguration, then write performance is maintained, but the duration of action (time for data migration) increases

Engineering Contradiction:
Improvesustained write performanceVSAvoiddata migration time
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent implements preliminary action by maintaining a pool of pre-identified spare blocks and pre-configured super block templates before defects occur. When a defective block is detected, the system can immediately initiate reconfiguration using pre-prepared resources, minimizing data migration time. This preliminary preparation ensures sustained write performance by reducing the duration of reconfiguration operations while maintaining the capability for frequent adaptations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11829623B2Using incomplete super blocks for increased write performance
Publication Date: 2023.11.28 MICRON TECHNOLOGY INC
  • US11829623B2 patent drawing
  • US11829623B2 patent drawing
  • US11829623B2 patent drawing

AI summary

A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.