Continuous-Time Incremental ADC with Feed-In Gain for Faster Conversion

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Solution Overview

Problem

Traditional continuous time incremental analog-to-digital converters (ADCs) suffer from long conversion times and significant linear and direct-current (DC) offset errors due to non-idealities, limiting their performance compared to discrete time counterparts.

Innovation Solution

A continuous-time incremental ADC is designed with a cascade configuration of resettable integrators and a feed-in gain element, where the output of each integrator is coupled to the input of a subsequent integrator, and a feed-in gain element is used between the input of the first-stage integrator and another integrator, reducing conversion time and matching the signal transfer function to that of a discrete-time ADC.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional continuous time incremental ADC architecture is used, then the ADC can operate in continuous time mode, but the conversion time becomes long

Engineering Contradiction:
Improveconversion speedVSAvoidconversion time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The ADC is divided into multiple cascaded integrator stages, where each stage processes a portion of the conversion. The feed-in gain element is strategically placed between specific integrator stages to optimize the signal processing distribution across segments, enabling parallel processing effects that reduce overall conversion time while maintaining continuous-time operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a feed-in gain element that adds an additional signal path dimension to the traditional integrator cascade. This gain element creates a parallel signal processing pathway that feeds directly into intermediate integrator stages, effectively adding a temporal dimension to the conversion process that accelerates convergence without sacrificing continuous-time architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If traditional continuous time incremental ADC is used, then the ADC structure is simple, but DC offset errors increase due to non-idealities

Engineering Contradiction:
ImproveADC structure complexityVSAvoidDC offset error
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The feed-in gain element acts as an intermediary component between the input signal and the integrator cascade. This intermediary element provides precise gain control that compensates for non-idealities in the integrator stages, reducing DC offset errors while maintaining the overall simplicity of the continuous-time architecture. The gain element serves as a mediator that corrects signal deviations without adding complex correction circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If more integrator stages are added to improve conversion accuracy, then measurement precision improves, but conversion time increases

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The feed-in gain element performs preliminary signal conditioning by applying precise gain adjustment at an intermediate stage of the integrator cascade. This preliminary action prepares the signal for subsequent integration stages, reducing the burden on each individual stage and enabling faster convergence. By pre-processing the signal with the gain element, the system achieves high accuracy without requiring excessive integration time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8698664B2Continuous-time incremental analog-to-digital converter
Publication Date: 2014.04.15 APPLE INC
  • US8698664B2 patent drawing
  • US8698664B2 patent drawing
  • US8698664B2 patent drawing

AI summary

In accordance with embodiments of the present disclosure, a continuous-time incremental analog-to-digital converter (ADC) may include a plurality of resettable integrators and a feed-in gain element. Each integrator may be configured to convert a sum of signals received at its input to a signal indicative of an integral over time of the sum of signals. The plurality of integrators may include a first-stage integrator configured to receive at its input the baseband signal and a final-stage integrator configured to produce at its output a final-stage analog signal. The plurality of integrators may be arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator. The feed-in gain element may be coupled between the input of the first-stage integrator and the input of another integrator of the plurality of integrators.