Incremental ADC Reset Timing to Prevent First-Stage Integrator Overshoot
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Solution Overview
Problem
Conventional incremental analog-to-digital converters (I-ADCs) experience overshoot or spike issues during reset, which can lead to a decrease in signal-to-noise and distortion ratio (SNDR) when internal circuits have voltage swing limits, especially when the voltage swing is significant.
Innovation Solution
Incorporating a reset signal processing module that generates a second reset signal with a later ending time point than the first reset signal by at least one clock cycle, specifically designed to reset the first-stage integrator module differently than other integrator and feedback modules, preventing overshoot or spike in the first-stage integrator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a first reset signal is used to reset all integrator modules and feedback modules simultaneously, then the reset operation is simple and fast, but overshoot or spike occurs in the first-stage integrator module causing SNDR degradation
Solution Approach 1:
The reset operation is segmented into two distinct phases: a first reset signal for feedback modules and a second reset signal for integrator modules. This segmentation allows differential resetting where the first-stage integrator module receives the second reset signal longer than other integrator modules, preventing overshoot while maintaining operational simplicity
Solution Approach 2:
The first-stage integrator module is given preliminary extended reset action through the second reset signal that lasts at least one clock cycle longer than the first reset signal. This preliminary extended resetting ensures the integrator is fully cleared before conversion starts, preventing subsequent overshoot that would degrade SNDR
2Device complexity
If the first-stage integrator module is reset with the same duration as other modules, then the reset process is uniform and simple, but voltage swing limits are exceeded causing distortion
Solution Approach 1:
Different reset durations are applied to different modules based on their specific requirements. The first-stage integrator module receives a longer second reset signal tailored to its vulnerability to overshoot, while other modules receive the standard first reset signal duration, optimizing each module's reset characteristics
3Reliability
If reset duration is extended for first-stage integrator module, then overshoot is prevented and SNDR is maintained, but reset operation complexity increases
Solution Approach 1:
A reset signal processing module acts as an intermediary that automatically generates the second reset signal based on the first reset signal. This intermediary handles the complexity of differential resetting, extending the reset duration for the first-stage integrator module without requiring complex manual control logic elsewhere in the system
Data Source
AI summary
An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.