Incremental Circuit Design Verification via Segmented RTL Simulation
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Solution Overview
Problem
The complexity of electronic circuit designs leads to increased likelihood of introducing bugs and errors during the verification process, particularly when transitioning from system-level modeling to Register Transfer Level (RTL) implementation, making it difficult to find and fix errors efficiently.
Innovation Solution
An incremental verification framework is introduced, where the design is verified in stages by translating and simulating subsets of modules from a system-level modeling language to RTL, using transactors to facilitate communication and data translation between different abstraction levels, thereby reducing the complexity and time required to identify and fix errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the design is verified at the RTL level using simulation comparison with C implementation, then the functionality can be verified, but the complexity and time required to find and fix errors increases significantly
Solution Approach 1:
The patent divides the verification process into multiple stages: system-level verification using C code, intermediate-level verification using mixed C-RTL models, and final RTL-level verification. This segmentation allows errors to be detected at multiple abstraction levels, reducing the complexity of finding and fixing bugs in the final RTL implementation.
Solution Approach 2:
The patent performs preliminary verification at the system level using C code before translating to RTL. By verifying the C implementation first and then verifying intermediate RTL modules against the verified C code, the system catches errors early in the design process, reducing the overall verification complexity and time required.
2Adaptability or versatility
If the design complexity increases to achieve desired functionality, then the functionality becomes more powerful, but the likelihood of introducing bugs increases
Solution Approach 1:
The patent segments the design into modular components that can be verified independently at different abstraction levels. This modularity allows complex functionality to be achieved through composition of simpler verified units, reducing the overall bug introduction likelihood while maintaining high functionality.
Solution Approach 2:
The patent implements a feedback mechanism where simulation results from RTL modules are compared against expected behavior from C implementations. This feedback loop allows continuous verification and correction of errors as the design complexity increases, maintaining reliability despite enhanced functionality.
3Reliability
If the verification process is performed thoroughly to ensure accuracy, then the reliability of the RTL implementation improves, but the time required for verification increases
Solution Approach 1:
The patent performs preliminary verification at the system level using C code before final RTL implementation. By catching and fixing errors during the C code verification phase and intermediate RTL verification phase, the system reduces the time required for final RTL verification while ensuring high accuracy.
Solution Approach 2:
The patent segments verification into parallelizable stages that can be performed sequentially with overlapping computations. This segmentation allows thorough verification without significant time penalty, as each stage builds upon previously verified components, reducing redundant verification work.
Data Source
AI summary
A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.