Incremental Clock Tree Planning with Cached Graphs
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Solution Overview
Problem
Current electronic design automation (EDA) systems for integrated circuits face inefficiencies in clock tree planning, requiring extensive computational resources and time due to the need for full clock tree synthesis during each design iteration, especially when minor changes or constraints are made, leading to increased turnaround time and resource consumption.
Innovation Solution
The implementation of an incremental clock tree planning method that caches and re-uses results from previous runs, automatically removes previous pin placements, and builds clock tree graphs for selected clocks based on cached initial graphs, reducing the need for full re-computation and minimizing design iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full clock tree synthesis is performed during each design iteration, then clock distribution accuracy is maintained, but computational time and resource consumption increase significantly
Solution Approach 1:
The system performs clock tree synthesis in advance during the initial design phase and caches the results. When design iterations occur, the cached results are reused instead of performing full synthesis again, unless the design changes significantly. This preliminary action eliminates redundant computational work while maintaining accuracy for unchanged portions of the design.
Solution Approach 2:
The system identifies and updates only the specific portions of the clock tree that are affected by design changes, rather than re-computing the entire clock tree. This localized update approach maintains clock distribution accuracy for changed areas while preserving the cached results for unchanged areas, significantly reducing computational time.
2Reliability
If full clock tree synthesis is performed during each design iteration, then clock network constraints are satisfied, but device complexity and resource consumption increase
Solution Approach 1:
The clock tree synthesis process is segmented into independent components that can be cached and reused. The system divides the design into unchanged and changed portions, applying full synthesis only to changed segments while reusing cached results for unchanged segments. This segmentation maintains constraint satisfaction while reducing overall system complexity.
Solution Approach 2:
The system creates cached copies of the clock tree synthesis results from the initial design. These copies are stored and reused during design iterations, eliminating the need to re-execute the complex synthesis algorithm unless necessary. The copying mechanism preserves constraint satisfaction while significantly simplifying the iterative design process.
3Productivity
If cached results are reused for incremental updates, then computational efficiency improves, but the need to manage and update cached data increases complexity
Solution Approach 1:
The system implements a feedback mechanism that monitors design changes and automatically determines whether cached results should be reused or updated. The feedback loop compares the current design state with the cached state, triggering full synthesis only when necessary. This automated feedback system manages cache complexity while maintaining high productivity.
Solution Approach 2:
The cache management system operates autonomously, automatically identifying which cached results are still valid and which need updating based on design changes. The system self-manages the complexity of cache validation and renewal without requiring manual intervention, thereby improving productivity while containing management complexity within the automated system.
Data Source
AI summary
A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.