Incremental Clock Tree Synthesis for Local Skew Optimization
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Solution Overview
Problem
Conventional clock tree synthesis techniques often fail to generate high-quality clock trees that satisfy timing, area, and leakage power constraints, leading to difficulties in achieving timing closure due to their focus on global clock skew rather than local clock skew optimization.
Innovation Solution
The approach partitions the circuit design into clock skew groups based on direct and transitive timing relationships, builds an initial clock tree to minimize worst-case clock skew, and optimizes it further to minimize local clock skew, allowing for incremental synthesis of clock trees in response to modifications, such as engineering change orders, by extending or rebuilding selected portions of the clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock tree synthesis techniques focus on global clock skew optimization, then overall clock distribution is improved, but local clock skew constraints are not satisfied and timing closure becomes difficult
Solution Approach 1:
The patent partitions the circuit design into multiple clock skew groups based on direct and transitive timing relationships between sequential circuit elements. Each group is then optimized independently for local clock skew, allowing precise control of local timing constraints while maintaining overall system functionality.
Solution Approach 2:
The invention applies different optimization strategies to different parts of the clock tree. By identifying clock skew groups with direct timing relationships and optimizing local clock skew within each group, the patent achieves precise local control without compromising global clock distribution performance.
2Reliability
If the entire clock tree is reconstructed after circuit modifications, then timing constraints can be re-optimized, but the process is time-consuming and disruptive
Solution Approach 1:
The patent enables incremental clock tree synthesis by segmenting the clock tree into clock skew groups. When circuit modifications occur, only the affected clock skew groups are identified and re-optimized, rather than reconstructing the entire clock tree. This significantly reduces the time and computational resources required while maintaining constraint satisfaction.
Solution Approach 2:
The invention pre-partitions the clock tree into clock skew groups based on timing relationships before modifications occur. This preliminary organization allows rapid identification of affected groups when changes are made, enabling quick local re-optimization without full reconstruction.
3Manufacturing precision
If clock tree synthesis optimizes worst case clock skew over all sequential elements, then global timing is improved, but local timing relationships are not adequately addressed
Solution Approach 1:
The patent divides the clock tree into multiple clock skew groups based on direct and transitive timing relationships. By optimizing worst case local clock skew within each group separately, the invention achieves precise clock skew control for local timing relationships while maintaining a manageable clock tree structure through hierarchical organization.
Data Source
AI summary
Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.