Incremental Glitch Analysis for IC Power Optimization
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Solution Overview
Problem
Existing electronic design automation (EDA) systems face challenges in efficiently optimizing glitch power consumption in integrated circuits, as glitch analysis is computationally expensive and time-consuming, especially during optimization processes.
Innovation Solution
The system employs incremental glitch analysis by determining a glitch-inducing window (GIW) and glitch factor for combinational logic gates, allowing for incremental modifications to be evaluated for their impact on glitch activity, thereby optimizing glitch power efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full glitch analysis is performed for every circuit modification, then glitch power optimization accuracy is improved, but computing time and resource consumption increase significantly
Solution Approach 1:
The patent segments the glitch analysis process into two parts: (1) calculating the glitch-inducing window (GIW) based on arrival time ranges of inputs, and (2) determining the glitch factor by comparing GIW with the logic gate's intrinsic delay. This segmentation allows the system to perform analysis incrementally rather than performing complete circuit simulation for every modification, significantly reducing computing time while maintaining optimization accuracy.
Solution Approach 2:
The patent performs preliminary calculation of the glitch-inducing window using arrival time ranges before determining the final glitch factor. By pre-computing the GIW based on input arrival time ranges and comparing it against the intrinsic delay, the system can quickly determine glitch behavior without performing full circuit simulation, thus reducing overall computing time while maintaining accuracy.
2Loss of energy
If comprehensive glitch analysis is performed during EDA optimization, then power consumption optimization is improved, but device complexity and computational overhead increase
Solution Approach 1:
The patent extracts the essential elements needed for glitch analysis: arrival time ranges of inputs and intrinsic delay of the logic gate. By taking out only these critical parameters and using them to calculate the glitch-inducing window and glitch factor, the system achieves power optimization without requiring complex full-circuit simulation, thus reducing computational complexity.
Solution Approach 2:
The patent changes the approach from simulating complete circuit behavior to analyzing specific parameters (arrival time ranges, intrinsic delay). By transforming the analysis into a parameter-based calculation of GIW and glitch factor, the system achieves power optimization with significantly reduced computational complexity, making it feasible to perform during EDA optimization.
3Productivity
If incremental glitch analysis is implemented, then computing resource requirements are reduced, but analysis accuracy may be compromised
Solution Approach 1:
The patent implements feedback by using the calculated glitch factor to determine whether to retain or revert circuit modifications. The glitch factor, derived from comparing the glitch-inducing window with intrinsic delay, provides feedback on the impact of modifications, enabling the optimization process to make informed decisions while maintaining accuracy through iterative refinement.
Solution Approach 2:
The patent applies partial action by analyzing only the essential parameters (arrival time ranges, intrinsic delay) rather than performing complete circuit simulation. This partial analysis of the glitch-inducing window and glitch factor provides sufficient accuracy for optimization decisions while significantly improving computing efficiency, avoiding the excessive action of full simulation.
Data Source
AI summary
A system and method for designing integrated circuits with incremental glitch analysis for efficient glitch power optimization, including determining a glitch factor for a combinational logic (CL) gate of a circuit based on arrival time ranges at first and second inputs of the CL gate and an internal delay of the CL gate, updating the glitch factor for the CL gate subsequent to a modification to the circuit design that impacts the CL gate, and determining whether to retain the modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.