Incremental NoC Topology Synthesis for Deadlock-Free Routing
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Solution Overview
Problem
Designing an optimal network-on-chip (NoC) that avoids routing and message-dependent deadlocks while efficiently utilizing existing connections and minimizing power and area overhead is a complex and time-consuming task, especially when modifying performance requirements or chip floorplans, leading to production delays.
Innovation Solution
A tool that generates NoC topologies incrementally, supporting regular network topologies, reuses existing segments, and determines connection order using mathematical optimization techniques or heuristics to ensure deadlock-free operation, preserving existing routes and minimizing latency and wire usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual NoC topology design is performed to avoid deadlocks and optimize performance, then deadlock-free operation and performance optimization are achieved, but design time and complexity increase significantly
Solution Approach 1:
The system performs automatic NoC topology synthesis where the computer automatically generates deadlock-free topologies using constraint-based algorithms, eliminating the need for manual design intervention while ensuring reliability requirements are met
Solution Approach 2:
The patent replaces manual mechanical design processes with automated computer-based algorithms that use mathematical optimization and constraint satisfaction to generate topologies, substituting human effort with computational methods
2Productivity
If manual NoC topology design is performed to optimize performance requirements, then optimal NoC configuration is achieved, but design complexity and time consumption increase
Solution Approach 1:
The system automatically optimizes NoC topologies by having the computer generate configurations that satisfy performance constraints through algorithmic exploration of the design space, eliminating manual optimization efforts
Solution Approach 2:
The patent uses parameter-based constraint specification where performance requirements are defined as constraints on topological parameters, and the automated synthesis process adjusts these parameters to find optimal configurations
3Adaptability or versatility
If existing NoC connections are modified to add new functionality, then adaptability is improved, but risk of introducing deadlocks increases
Solution Approach 1:
The system performs preliminary deadlock analysis and constraint verification before finalizing topology modifications, ensuring that adaptability changes do not compromise deadlock-free operation
Solution Approach 2:
The automated synthesis process incorporates feedback loops that verify deadlock constraints during topology generation, allowing the system to detect and correct potential deadlock conditions before they occur
4Reliability
If comprehensive deadlock avoidance checks are performed during topology synthesis, then routing-dependent deadlocks are prevented, but synthesis time increases
Solution Approach 1:
The system performs preliminary constraint formulation and validation before detailed topology synthesis, pre-processing deadlock avoidance requirements into checkable constraints that speed up the main synthesis process
Solution Approach 2:
The patent replaces time-consuming manual deadlock analysis with automated algorithmic verification that efficiently checks routing-dependent deadlock constraints during synthetic generation
Data Source
AI summary
A tool is disclosed for using custom subnetwork description during generation and synthesis of the network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and transformation of a deadlock-free NoC. The NoC topology is translated into an existing segment; reusing the existing segment in a new route and generating the deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.