Incremental NoC Synthesis Tool for Deadlock-Free Network Topologies
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Solution Overview
Problem
Designing an optimal network-on-chip (NoC) that avoids routing and message-dependent deadlocks while minimizing power and area overhead is challenging, especially when introducing new connections, as current methods require complex and time-consuming redesigns in response to changes in performance requirements or chip floorplan modifications.
Innovation Solution
A tool that generates NoC topology incrementally, synthesizing new connections one at a time, reusing existing segments, and supporting regular network topologies like Mesh networks, with mathematical optimization techniques to determine the synthesis order and ensure deadlock-free routes, while preserving existing routes and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional NoC design methods are used to accommodate new connections, then connectivity requirements are met, but the design process becomes time-consuming and requires frequent redesigns
Solution Approach 1:
The patent implements a dynamic incremental synthesis approach where the NoC topology is not fixed but can be continuously modified by adding new connections. The system dynamically updates the topology by synthesizing new connections one at a time while preserving existing routes, allowing the design to adapt to changing requirements without complete redesign.
Solution Approach 2:
The patent performs preliminary actions by establishing a foundation of existing connections and routes before adding new ones. The incremental synthesis methodology prepares the topology in advance by maintaining a set of existing connections that serve as the basis for future expansions, reducing the time needed for subsequent modifications.
2Reliability
If complex routing is implemented to avoid deadlocks, then deadlock-free operation is achieved, but power and area overhead increase
Solution Approach 1:
The patent segments the routing problem by treating each connection synthesis independently while maintaining global deadlock-free properties. By dividing the topology into manageable connection units and synthesizing them incrementally, the system achieves deadlock avoidance without requiring complex global routing schemes that would increase power and area overhead.
Solution Approach 2:
The patent introduces an intermediary synthesis methodology that mediates between connectivity requirements and deadlock avoidance. The incremental synthesis process acts as an intermediary mechanism that automatically ensures deadlock-free operation while minimizing the complexity of routing paths, thereby reducing power and area overhead compared to traditional complex routing schemes.
3Adaptability or versatility
If comprehensive NoC redesign is performed to meet new requirements, then performance requirements are fulfilled, but production delays occur
Solution Approach 1:
The system transitions from static comprehensive redesign to dynamic incremental updates. Each new connection is synthesized independently and integrated into the existing topology, allowing the design to evolve continuously without stopping production or performing time-consuming complete redesigns.
Solution Approach 2:
The patent recovers and preserves existing valid connections and routes when adding new ones. Instead of discarding the entire design for redesign, the incremental synthesis methodology recovers the existing topology structure and builds upon it, significantly reducing the time and resources needed to meet new performance requirements.
4Adaptability or versatility
If new connections are added to existing NoC, then connectivity is enhanced, but routing deadlocks may be introduced
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing deadlock formation during the connection synthesis process. The incremental synthesis methodology incorporates deadlock avoidance checks and constraints before new connections are fully integrated, counteracting potential deadlock issues before they can manifest in the enhanced connectivity structure.
Data Source
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AI summary
A tool is disclosed for using custom subnetwork description during generation and synthesis of the network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and transformation of a deadlock-free NoC. The NoC topology is translated into an existing segment; reusing the existing segment in a new route and generating the deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.