Incremental Path-Based Analysis for IC Timing Optimization
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Solution Overview
Problem
Current timing analysis methods in integrated circuit design, such as static timing analysis (STA), are conservative and often lead to pessimistic results, requiring increased power consumption, area, and reduced speed due to their inability to accurately account for process variations, necessitating the incorporation of more accurate but slower path-based timing analysis (PBA) during the verification phase rather than optimization.
Innovation Solution
Incorporating an incremental path-based analysis (PBA) into the place and route optimization phase, using a PBA database and multithreaded programming to reduce analysis time and enable faster, more accurate timing optimization, thereby reducing elapsed time and improving circuit performance with minimal memory and CPU overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If path-based timing analysis (PBA) is used during verification phase, then measurement precision is improved, but productivity deteriorates due to slower analysis time
Solution Approach 1:
The patent segments the circuit into multiple threads for parallel processing during PBA. Each thread independently analyzes specific timing paths, allowing the overall analysis to be distributed across multiple CPU cores. This segmentation maintains the accuracy of PBA while reducing total analysis time through concurrent execution.
Solution Approach 2:
The patent performs preliminary graph-based timing analysis (GBA) before PBA to identify critical paths. By pre-processing the circuit to determine which paths are most timing-critical, the system can focus PBA resources on those specific paths rather than analyzing all possible paths, thereby maintaining precision while improving productivity.
2Manufacturing precision
If path-based timing analysis (PBA) is used for circuit optimization, then manufacturing precision is improved, but loss of time increases due to computational complexity
Solution Approach 1:
The optimization process is segmented into multiple independent threads that can execute in parallel. Each thread handles specific optimization tasks for different circuit regions or timing paths, maintaining high precision in the overall optimization while reducing total elapsed time through concurrent processing.
Solution Approach 2:
The patent applies PBA selectively to only those circuit paths that require optimization rather than performing exhaustive PBA on the entire circuit. By identifying and focusing on critical paths that need timing optimization, the system achieves high manufacturing precision for the most important paths while avoiding unnecessary computational overhead.
3Productivity
If traditional graph-based analysis (GBA) is used, then productivity is maintained with faster analysis, but measurement precision deteriorates leading to pessimistic results
Solution Approach 1:
The patent merges GBA and PBA into a hybrid approach where GBA provides the foundational timing analysis and identifies critical paths, while PBA is applied specifically to those critical paths to remove pessimism. This combination maintains the speed advantage of GBA while incorporating the precision benefits of PBA where most needed.
Solution Approach 2:
Instead of applying uniform analysis methodology throughout the entire circuit, the patent applies different analysis qualities to different regions. GBA is used for general timing analysis across all paths, while PBA is applied locally to critical paths where higher precision is needed to remove pessimism, thereby optimizing the balance between productivity and measurement precision.
Data Source
AI summary
A database is constructed based on a batch PBA performed on a plurality of paths of an integrated circuit. A local PBA is performed on a portion of a selected path. A selected optimization move is identified on the portion of the selected path, based on a result of the local PBA that best meets a set of constraints. A path-wide PBA is performed for an updated path that is based on the selected path incorporating the selected optimization move. The selected optimization move is committed in a netlist associated with the integrated circuit.