Incremental Placement for Critical Circuit Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional circuit design optimization techniques often result in suboptimal performance in certain regions due to global optimization approaches, leading to time-consuming iterative processes between re-synthesis and placement tools, particularly when trying to balance wire length and timing requirements.
Innovation Solution
A method that identifies critical regions within a circuit design post-placement, allowing for localized re-synthesis and relocation of blocks within those regions using cost functions and placement techniques, while preserving predetermined functionality, to optimize timing and wire length without re-synthesizing or re-placing the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If global optimization is performed on the entire circuit design during physical synthesis, then total wire length is reduced and routing resources are conserved, but timing requirements in certain regions are not met and the optimization process becomes time-consuming
Solution Approach 1:
The patent divides the circuit design into multiple regions and identifies critical regions that require optimization. Instead of performing global optimization on the entire circuit, the method segments the problem by focusing placement optimization specifically on critical regions where timing requirements are not met, while leaving non-critical regions unchanged. This segmentation allows simultaneous optimization of wire length in critical areas without compromising overall timing requirements.
Solution Approach 2:
The patent applies local quality by performing placement optimization with different objectives for different regions of the circuit. In critical regions, the optimization focuses on meeting timing requirements, while in non-critical regions, the existing placement is preserved. This localized approach ensures that timing-critical portions receive targeted optimization without unnecessarily modifying well-performing regions, thereby improving overall circuit reliability.
2Ease of manufacture
If global optimization is performed on the entire circuit design during physical synthesis, then routing resources are conserved, but the optimization process becomes time-consuming due to multiple iterations
Solution Approach 1:
The patent segments the optimization process to focus only on critical regions rather than the entire circuit design. By identifying and isolating critical regions where timing requirements are not met, the method reduces the scope of placement optimization from global to local. This segmentation significantly reduces computation time and the number of iterations required, while still achieving effective utilization of routing resources in the critical areas.
Solution Approach 2:
The patent applies partial action by performing placement optimization only on critical regions rather than the entire circuit. This partial optimization approach is sufficient to meet timing requirements without the need for exhaustive global optimization. The method achieves adequate routing resource utilization by focusing computational effort only where needed, thereby reducing overall optimization time while maintaining manufacturing ease.
3Length of moving object
If placement optimization focuses on reducing wire length, then routing resources are conserved, but timing characteristics in certain regions deteriorate
Solution Approach 1:
The patent applies local quality by implementing region-specific optimization objectives. In critical regions where timing requirements are not met, the placement optimization prioritizes timing characteristics over wire length minimization. In non-critical regions, the existing placement that achieves good wire length is preserved. This localized differentiation of optimization goals allows the circuit to achieve both reduced wire length in non-critical areas and improved timing characteristics in critical areas.
Solution Approach 2:
The patent segments the circuit into critical and non-critical regions, applying different optimization strategies to each segment. In critical regions, the optimization focuses on meeting timing requirements even if it increases wire length locally. In non-critical regions, wire length minimization continues to be the primary objective. This segmentation resolves the contradiction by allowing wire length reduction where it does not impact timing, while protecting timing-critical regions from excessive wire length penalties.
Data Source
AI summary
A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.