Incremental Power Throttling for Memory Subsystems

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Solution Overview

Problem

Conventional memory systems face inefficiencies in power management due to the allocation of fixed power credits for memory operations, leading to unnecessary blocking of smaller credit operations and increased latency.

Innovation Solution

Implementing incremental power throttling on a memory system using power credit allocations and memory operation progress tracking, allowing for pausing and resuming of operations and adjusting power credits based on operation progress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed power credits are allocated for memory operations, then power management is simplified, but smaller credit operations are blocked and latency increases

Engineering Contradiction:
Improvepower management complexityVSAvoidoperation throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments power credits into incremental units that can be allocated and released in smaller portions. Instead of allocating fixed power credits for entire operations, the system allocates credits incrementally as operations progress, allowing smaller operations to access freed credits and reducing blocking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic power credit allocation where credit amounts adjust based on operation progress. As memory operations complete stages, previously allocated credits are released back to the pool, creating a dynamic system that adapts to current workload needs rather than using static fixed allocations.

Inventive Principle:
Principle #15Dynamics

2Power

If fixed power credits are allocated for memory operations, then power budget control is maintained, but latency outliers increase

Engineering Contradiction:
Improvepower budget controlVSAvoidoperation latency
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent employs feedback mechanisms where the system continuously monitors operation progress and uses this information to determine when to release power credits. As operations advance through stages, the system receives feedback on completion status and releases appropriate credit amounts, creating a closed-loop control system that maintains power budget while reducing latency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the parameter of power credit allocation from fixed to variable based on operation progress. By adjusting credit allocation dynamically according to how far operations have progressed, the system maintains overall power budget control while allowing smaller operations to proceed without excessive waiting time.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If fine granularity power credits are implemented, then operation scheduling flexibility improves, but power management complexity increases

Engineering Contradiction:
Improveoperation scheduling flexibilityVSAvoidpower management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments power credits into fine-grained incremental units tied to specific operation stages. This segmentation enables flexible scheduling as operations can be paused and resumed at boundaries where credits are naturally released, providing adaptability without requiring complex arbitrary credit allocations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent prepares power credit releases in advance at known operation milestones. By pre-determining when credits will be released based on operation progress stages, the system achieves scheduling flexibility without implementing complex real-time decision-making mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250147669A1Incremental power throttling on memory system
Publication Date: 2025.05.08 MICRON TECHNOLOGY INC
  • US20250147669A1 patent drawing
  • US20250147669A1 patent drawing
  • US20250147669A1 patent drawing

AI summary

Various embodiments provide for incremental power throttling on a memory system, such as a memory sub-system. In particular, for some embodiments, incremental power throttling is implemented on a memory system using one or more power credit allocations and memory operation progress tracking.