Incremental Resynthesis for FPGA Netlist Optimization
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Solution Overview
Problem
Designing large systems on complex target devices like FPGAs and ASICs requires significant time for compilation procedures, especially when only localized changes are made, leading to undesirable re-processing of unmodified portions and potential timing issues due to the heuristic nature of CAD algorithms.
Innovation Solution
A method and apparatus for fast incremental resynthesis that reuses synthesis results from previous compilations to minimize the logic that needs to be resynthesized, preserving unchanged logic and using timing information from previous compilations to guide the synthesis of changed regions, thereby reducing runtime and maintaining timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire system is re-compiled after localized changes, then completeness of design verification is improved, but compilation time increases significantly
Solution Approach 1:
The patent segments the design into modified and unmodified regions, performing synthesis only on the modified region while preserving the unmodified region from the previous compilation. This segmentation allows the EDA tool to verify the complete design (maintaining reliability) while avoiding redundant processing of unchanged portions (reducing compilation time).
Solution Approach 2:
The patent performs preliminary identification of modified regions before initiating full re-compilation. By detecting changes in the netlist structure and identifying boundary regions in advance, the system prepares the design for incremental synthesis, preventing the need to re-process entire unmodified portions and thus reducing compilation time while maintaining verification completeness.
2Manufacturing precision
If the entire system is processed from scratch, then timing closure can be achieved, but the heuristic nature of CAD algorithms may unfavorably change timing results of unmodified portions
Solution Approach 1:
The patent applies local quality by treating modified and unmodified regions differently. Unmodified regions preserve their previously optimized timing characteristics and structure, while modified regions undergo new synthesis and timing optimization. This selective approach maintains the stability of timing results for unmodified portions while achieving timing closure for the complete design through focused optimization of changed areas.
3Adaptability or versatility
If localized changes are made to the design, then design flexibility is improved, but re-compilation of the entire system becomes undesirable
Solution Approach 1:
The patent segments the design into modified and unmodified regions, performing synthesis only on the modified region while preserving the unmodified region from the previous compilation. This segmentation allows the EDA tool to verify the complete design (maintaining reliability) while avoiding redundant processing of unchanged portions (reducing compilation time).
Solution Approach 2:
The patent performs preliminary identification of modified regions before initiating full re-compilation. By detecting changes in the netlist structure and identifying boundary regions in advance, the system prepares the design for incremental synthesis, preventing the need to re-process entire unmodified portions and thus reducing compilation time while maintaining verification completeness.
Data Source
AI summary
A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.