Incremental Speculative Merging for Verification Restart Cost Reduction
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Solution Overview
Problem
Current state variable model synthesis and verification processes are computationally expensive due to the need to restart and discard verification results when invalid merge candidates are found, leading to high costs in refining and re-verifying equivalence.
Innovation Solution
The implementation of an incremental speculative merge system that allows for the undoing of invalid merges and the reuse of verification results across refinements, using a multiplexer to switch between valid and invalid gate outputs during equivalence testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If speculative merging is performed to reduce verification proof obligation size, then verification speed is improved, but when invalid merge candidates are found the entire verification problem must be recast resulting in high restart costs
Solution Approach 1:
The patent segments the verification process by introducing switchable units (multiplexers) that allow individual merge candidates to be independently activated or deactivated. Instead of treating the entire verification problem as a single unit that must be recast upon failure, the system divides it into manageable segments corresponding to individual merge candidates, enabling selective refinement without complete restart.
Solution Approach 2:
The patent introduces dynamic switching capability through multiplexers that can change their selection based on verification results. The switchable units allow the verification system to dynamically adapt by enabling valid merges and disabling invalid ones, transforming a static verification process into a dynamic one that learns from and adapts to verification outcomes without complete restart.
2Ease of manufacture
If equivalent gates are merged to reduce circuit size and power consumption, then manufacturing cost is reduced, but verification complexity increases due to need to prove equivalence
Solution Approach 1:
The patent applies preliminary action by performing speculative merging before complete equivalence verification. The system proactively merges gates based on initial analysis, then uses the switchable verification framework to validate or reject these merges incrementally, rather than requiring complete equivalence proof before any merging action.
Solution Approach 2:
The patent introduces switchable units (multiplexers) as intermediaries between merged gate candidates and the rest of the circuit. These intermediary elements allow the verification system to test equivalence hypotheses without permanently committing to merges, reducing verification complexity by providing a safe testing mechanism.
3Reliability
If complete equivalence verification is performed before merging, then merge accuracy is improved, but computational resources and time are excessively consumed
Solution Approach 1:
The patent applies partial action by performing incomplete or speculative merging based on preliminary analysis rather than complete equivalence verification. The switchable verification framework then allows incremental validation of these partial merges, achieving sufficient accuracy for practical purposes without the overhead of exhaustive verification.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the switchable verification framework that allows verification to continue and accumulate results across multiple refinement iterations. Valid merge candidates identified in earlier iterations remain enabled and their verification results are preserved, allowing the process to build upon previous work rather than restarting.
Data Source
AI summary
An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g1i and g2i, and the fanout references of g1i and g2i are provided to a controllable multiplexer set to output g1i. Upon determining nonequivalence of g2i, of failing to proved equivalence, the multiplexer is switched to output the g1i fanout reference, thus undoing the incremental speculative merge.