Incremental Synthesis Flow for IC Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital design synthesis methods are time-consuming and inefficient, especially during the timing/power closure cycle, as they require triggering synthesis over the whole design even for small changes, leading to delayed feedback and degradation in design quality.
Innovation Solution
An interactive incremental synthesis flow framework that identifies invariant cones in the design, allowing only the modified regions to be re-synthesized, reducing the synthesis time by focusing on near-real-time processing and maintaining quality of results (QoR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If full synthesis is triggered over the whole design even for small changes, then synthesis completeness is maintained, but synthesis time increases significantly
Solution Approach 1:
The patent partitions the design into invariant cone regions based on functional boundaries. When a change is made, only the affected partition is re-synthesized rather than the entire design. This segmentation allows selective synthesis of modified regions while maintaining overall design completeness, resolving the contradiction between synthesis thoroughness and time consumption.
Solution Approach 2:
The patent applies different synthesis strategies to different regions: invariant cones are re-synthesized locally when changed, while unchanged regions are preserved from previous synthesis results. This local quality approach ensures that synthesis completeness is maintained for modified areas without unnecessarily re-processing unchanged areas, thereby reducing total synthesis time.
2Loss of time
If incremental synthesis is performed on small modified regions, then synthesis time is reduced, but design quality may deteriorate due to artificial partitioning
Solution Approach 1:
The patent performs a preliminary full synthesis to establish baseline quality metrics and identify invariant cones before incremental changes. This preliminary action creates a reference quality standard that subsequent incremental syntheses can measure against, ensuring that quality deterioration is detected and prevented while still benefiting from time reductions.
Solution Approach 2:
The patent implements feedback mechanisms that compare incremental synthesis results against the preliminary full synthesis baseline. When quality degradation is detected in modified regions, the system can trigger additional optimization passes or adjust partitioning strategies, ensuring that design quality is maintained while still achieving significant time reductions through selective re-synthesis.
3Manufacturing precision
If frequent synthesis iterations are performed for design optimization, then design quality improves, but time consumption increases due to repeated full synthesis
Solution Approach 1:
The patent enables frequent synthesis iterations by segmenting the design into invariant cone partitions. Each iteration only re-synthesizes the specific partition that was modified, allowing designers to perform multiple optimization cycles per day without the prohibitive time cost of repeated full synthesis. This maintains design quality improvement while dramatically increasing iteration speed.
Solution Approach 2:
The patent makes the synthesis process dynamic by adaptively determining which partitions need re-synthesis based on the specific changes made. Rather than following a fixed full-synthesis schedule, the system dynamically adjusts the synthesis scope to match actual design modifications, enabling frequent iterations when changes are small and maintaining productivity while improving design quality over time.
Data Source
AI summary
An interactive incremental synthesis flow for integrated circuit design includes performing a full synthesis [304] of a circuit design to produce an elaborated netlist and synthesized netlist; based on the elaborated netlist and synthesized netlist, automatically partitioning [306] the circuit design into invariant cone regions whose functionality do not change during synthesis; and performing an incremental synthesis [308] each time a change is made to the circuit design. The incremental synthesis includes performing an elaboration [318] of a module of the design containing the change; performing a structural comparison [310] between the elaborated netlist and a modified elaborated netlist to identify modified invariant cones containing the change; synthesizing [312] gates contained in the modified invariant cones; deleting from the synthesized netlist the gates contained within the modified invariant cones that have been changed; and inserting [314] the synthesized gates corresponding to the modified invariant cones into the synthesized netlist.