Incremental Physical Synthesis Legalization for IC Timing
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Solution Overview
Problem
Conventional integrated circuit design processes face inefficiencies due to excessive runtimes and failure to meet timing constraints during legalization, as physical synthesis changes are often scrapped or lead to deteriorated timing, especially when legalization is performed after placement.
Innovation Solution
Implementing multiple incremental physical synthesis, timing optimization, and legalization operations before generating configuration data, allowing for dynamic adjustments and incremental legalization to ensure legality and optimal timing, with the ability to move logic blocks to satisfy both timing and legality constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical synthesis is performed before or after placement phase with legalization performed after post-placement physical synthesis, then legality rules can be satisfied, but timing constraints deteriorate and excessive runtimes occur
Solution Approach 1:
The patent divides the physical synthesis process into multiple incremental stages, where each stage performs limited synthesis operations followed by selective legalization. This segmentation allows the system to process only the necessary portions of the design at each step, reducing overall runtime while maintaining legality satisfaction through iterative refinement.
Solution Approach 2:
The patent performs preliminary legalization checks and adjustments during the physical synthesis process itself, rather than waiting until after completion. By addressing legality issues incrementally as they arise, the system prevents accumulated violations that would require extensive rework later, thereby reducing total processing time.
2Reliability
If physical synthesis is performed before or after placement phase with legalization performed after post-placement physical synthesis, then legality rules can be satisfied, but timing constraints deteriorate
Solution Approach 1:
The patent implements feedback mechanisms where timing analysis results from each incremental synthesis stage are used to guide subsequent synthesis decisions. The system continuously monitors timing constraints and adjusts the synthesis strategy accordingly, ensuring that timing degradation is prevented while maintaining legality through iterative optimization.
Solution Approach 2:
The patent employs dynamic adjustment of synthesis parameters and legalization strategies based on real-time timing and legality assessments. The system adapts its approach during the design process, modifying placement and routing decisions dynamically to satisfy both timing constraints and legality rules, rather than following a fixed sequential process.
3Reliability
If legalization is performed after post-placement physical synthesis, then all changes can be validated, but changes are scrapped when only a small subset causes legalization errors
Solution Approach 1:
The patent performs partial legalization validation at each incremental synthesis stage rather than waiting for complete synthesis. By validating and correcting legality issues in smaller portions, the system identifies and resolves problems in a limited subset of changes at each step, preventing the accumulation of numerous violations that would require scrapping large portions of the design.
Solution Approach 2:
The patent maintains continuous incremental synthesis and legalization operations, where each stage builds upon the previous successful changes. This continuous process preserves accumulated valid modifications while systematically addressing legality issues, ensuring that productive work is not lost through repeated scrapping and restarting of the entire design.
Data Source
AI summary
Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization constraints while improving the timing of the design. If the legalization constraints are not satisfied, the design equipment may recursively move non-critical logic blocks to new locations while ensuring that the legalization and timing constraints are satisfied for each move such that the timing of the design is improved. This may be repeated in multiple rounds of adjustment. A netlist may be generated after the moves are performed. The configuration data may be generated based on the netlist.