Indented Gate Structure for FinFET Shorting Prevention
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Solution Overview
Problem
Conventional FinFET fabrication techniques face challenges in preventing shorting of adjacent metal gates and undesirable fin top damage due to non-uniform etching and gate footing, which affects the integration and performance of multi-gate devices.
Innovation Solution
A semiconductor structure with an indented gate segment and a uniform undercut at the interface with the substrate/fin, along with a high conductivity layer, is introduced to prevent shorting and fin top damage, featuring a gate structure with a first segment sandwiched between dielectric sidewalls and a second segment with a greater dimension to create an undercut region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FinFET fabrication techniques are used, then multi-gate devices can be formed, but adjacent metal gates may short and fin top damage occurs due to non-uniform etching and gate footing
Solution Approach 1:
The gate structure is divided into two distinct segments: a first gate segment formed over the fin structure, and a second gate segment formed over the isolation feature. This segmentation prevents the metal gates from shorting by creating a physical separation between adjacent gates, while still maintaining the multi-gate device functionality through the wrapped-around gate configuration.
Solution Approach 2:
An intermediary material layer is introduced between the fin structure and the first gate segment to prevent direct contact and potential shorting. This intermediary layer acts as a barrier that eliminates the gate footing problem while allowing the gate structure to maintain its wrapping function around the fin.
2Adaptability or versatility
If conventional FinFET fabrication techniques are used, then multi-gate devices can be formed, but fin top damage occurs due to non-uniform etching
Solution Approach 1:
The gate structure is designed with a preliminary configuration where the first gate segment is formed with specific dimensions and positioning before subsequent processing steps. This preliminary action ensures that the gate structure is already optimized to prevent fin top damage during later etching and fabrication processes, maintaining fin top integrity throughout manufacturing.
Solution Approach 2:
The gate structure parameters are optimized by controlling the dimensions of the first gate segment relative to the fin structure, and positioning the second gate segment over the isolation feature. These parameter changes create a uniform undercut that prevents non-uniform etching damage to the fin top while maintaining multi-gate device functionality.
3Productivity
If gate structures are made smaller to reduce IC size, then integration density improves, but gate shorting between adjacent FinFETs becomes more likely
Solution Approach 1:
By segmenting the gate structure into two distinct parts (first gate segment over fin, second gate segment over isolation feature), the design enables closer spacing of adjacent FinFETs without causing gate shorting. This segmentation maintains gate isolation even at smaller dimensions, allowing higher integration density while preserving reliability.
Solution Approach 2:
The intermediary material layer and the isolation feature serve as mediators that maintain electrical isolation between adjacent gates even when the overall device size is reduced. This allows integration density to increase while gate shorting is prevented through the intermediary barrier.
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.