Independent C3 State Control for Multiprocessor Power Management
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Solution Overview
Problem
In multiprocessor systems, existing power management technologies, such as ACPI, force all CPUs to enter or leave the C3 state synchronously, limiting the ability to achieve the most power-saving status due to the need for simultaneous CPU state changes, which results in increased power consumption.
Innovation Solution
A power management device and method that includes checking units and recording units to independently manage the power states of each CPU by checking event correspondence, recording events, and sending commands to shut down or wake up CPUs, allowing them to enter or leave the C3 state independently without affecting other CPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the arbiter is shut down to stop transmitting events when one CPU enters C3 state, then power consumption is reduced, but all CPUs are forced to leave C3 state synchronously, preventing optimal power-saving status
Solution Approach 1:
The patent divides the system into independent per-CPU arbiters (first arbiter for first CPU, second arbiter for second CPU) instead of a shared arbiter. This segmentation allows each CPU to independently control its own arbiter's shutdown state, enabling one CPU to enter C3 state while another remains active without forcing synchronous state changes.
Solution Approach 2:
The patent introduces recording units that record events and checking units that check whether CPUs are in C3 state. These intermediaries manage the interaction between CPUs and arbiters, allowing the system to maintain event transmission to active CPUs while preventing transmission to sleeping CPUs, thus enabling asynchronous C3 state transitions.
2Device complexity
If a shared arbiter is used to manage events for multiple CPUs, then device complexity is reduced, but all CPUs must enter or leave C3 state synchronously, limiting power-saving capability
Solution Approach 1:
Instead of using a single shared arbiter, the patent segments the arbitration function into multiple independent arbiters, each dedicated to a specific CPU. This increases structural complexity slightly but enables asynchronous power management where each CPU can independently enter or leave C3 state based on its own workload, optimizing overall power consumption.
3Reliability
If the arbiter continues to send events to CPUs in C3 state, then event processing is maintained, but the CPU not in C3 state experiences problems due to mutual bus contention
Solution Approach 1:
The patent introduces checking units that check whether a CPU is in C3 state before allowing event transmission through the arbiter. This intermediary checking mechanism prevents events from being sent to sleeping CPUs, avoiding bus contention issues while ensuring events are only transmitted to active CPUs that can properly process them.
Solution Approach 2:
The system uses feedback from the checking units about CPU power states to control arbiter behavior. When a CPU is detected to be in C3 state, the checking unit provides feedback that prevents the arbiter from transmitting events to that CPU, thereby avoiding bus contention problems while maintaining reliable event processing for active CPUs.
Data Source
AI summary
A power management device for multiprocessor systems and method thereof applied to force individual processor entering or leaving of a C3 state are disclosed. The device includes at least one checking unit, a plurality of recording units and a plurality of arbiters. The checking unit receives an event from a peripheral device, checks which processor the event corresponds and sends a checking signal. The event is received and recorded by one of the recording units according to the checking signal. Once the recording unit has no record of the received event, the corresponding processor turns the corresponding arbiter off and sends an entering C3 state command. A first control signal is sent to the processor according to the entering C3 state command so as to force the processor into the C3 state.