Independent Clock Sources for Stacked Memory Interfaces
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Solution Overview
Problem
High-speed inter-chip interfaces in stacked package-on-package systems suffer from clock jitter and clock-to-signal skews due to physical segmentation, limiting system frequency and performance.
Innovation Solution
Implementing independent clock sources and inter-chip interfaces for each memory part within the logic chip, allowing each to operate independently and reducing signal path length, thereby mitigating clock jitter and skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single shared inter-chip interface is used for multiple memory parts, then device complexity is reduced, but clock signal jitter and skew increase due to physical segmentation
Solution Approach 1:
The patent divides the single shared inter-chip interface into multiple independent interfaces, with each memory part having its own dedicated interface to the logic chip. This segmentation eliminates the clock jitter and skew problems caused by physical segmentation in shared interfaces, as each interface has its own dedicated signal paths and clock distribution networks.
2Reliability
If independent clock sources are provided for each memory part, then timing accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent provides separate clock sources for each memory part, with each clock source dedicated to its corresponding memory interface. This ensures that clock signals for different memory parts are independent and do not suffer from jitter and skew caused by sharing a common clock distribution network.
3Reliability
If independent clock sources are used for each memory part, then clock jitter and skew are reduced, but power consumption increases
Solution Approach 1:
The patent implements separate clock sources and independent interfaces for each memory part, which reduces clock jitter and skew. While this increases power consumption compared to a shared interface, it enables higher clock frequencies and improved timing accuracy that are critical for high-performance memory systems.
Data Source
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AI summary
In an embodiment, a stacked package-on-package system has a memory die (102; 104) and a logic die (106). The memory die comprises a first memory (306) and a second memory (308), each operated independently of the other, and each having an inter-chip interface (310; 312) electrically connected to the logic die. The logic die has two independent clock sources (318; 322), one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.