Independent Coherence Nodes With Pooled Memory Access
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Solution Overview
Problem
Data centers face inefficiencies due to resource stranding, where a subset of compute nodes are resource-intensive while others sit idle, leading to low total resource utilization and resource-constrained workloads.
Innovation Solution
Implement a computing device with independently coherent compute nodes and a central IO die that manages pooled memory and IO resources, allowing flexible access and dynamic allocation of memory units across nodes, including natively-attached and disaggregated volatile memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single coherent domain is used across all compute nodes, then cache coherence is maintained, but system scalability is limited and memory access latency increases
Solution Approach 1:
The patent divides the coherent domain into separate coherence domains for each compute node. Each compute node has its own coherence domain with a dedicated home agent, allowing independent cache coherence management. This segmentation enables the system to scale by adding more compute nodes without requiring a single large coherent domain, thus resolving the contradiction between maintaining cache coherence and achieving system scalability.
2Reliability
If a single coherent domain is used across all compute nodes, then cache coherence is maintained, but memory access latency increases
Solution Approach 1:
By segmenting the coherent domain into node-specific domains, memory access latency is reduced because each compute node can access its locally attached volatile memory units through direct memory access without traversing the entire distributed memory space. The home agent manages cache coherence within each domain while allowing faster local memory accesses.
Solution Approach 2:
The home agent acts as an intermediary between compute nodes and the central IO die. It manages memory access requests by mapping them to appropriate volatile memory units, enabling more efficient memory access patterns and reducing latency compared to a flat coherent domain architecture.
3Productivity
If natively-attached volatile memory units are used, then memory bandwidth is increased, but device complexity increases
Solution Approach 1:
The memory subsystem is segmented into natively-attached volatile memory units connected to each compute node via memory controllers. This segmentation provides high memory bandwidth for each node while the central IO die provides a unified interface for I/O operations, managing the complexity through modular architecture.
Solution Approach 2:
The central IO die serves as an intermediary that manages the complexity of connecting multiple compute nodes with natively-attached volatile memory units. It provides a centralized control point for memory access coordination while allowing each node to benefit from high-speed local memory access.
4Productivity
If compute nodes are added to increase processing power, then computational capability is improved, but inter-node communication overhead increases
Solution Approach 1:
By implementing separate coherence domains for each compute node with dedicated home agents, the system enables more efficient inter-node communication. Each node can manage its own cache coherence independently, reducing the communication overhead associated with maintaining coherence across a large distributed domain while still enabling parallel processing.
Data Source
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AI summary
A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively attached volatile memory units.