Independent-Gate Semiconductor Structure for UIS Over-Voltage Clamping
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Solution Overview
Problem
Power semiconductor devices face challenges during Unclamped Inductive Switching (UIS), where high voltage and current stresses can lead to catastrophic failure due to the buildup of stored magnetic energy, particularly in silicon MOSFETs and wide bandgap materials like gallium nitride, which lack intrinsic body diodes and are prone to destructive voltage increases.
Innovation Solution
The implementation of semiconductor devices with multiple independent gates, where a primary gate controls the majority of cells, and an auxiliary gate, electrically isolated from the primary gate, is used for over-voltage protection. This configuration includes a plurality of cells with separate gate electrodes for the primary and auxiliary gates, allowing for parallel sourcing and draining, and can incorporate active clamp circuitry to manage peak voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate controls all cells in the semiconductor device, then the device structure is simple and manufacturing is easier, but the device lacks over-voltage protection capability and is vulnerable to catastrophic failure during UIS events
Solution Approach 1:
The gate structure is segmented into two electrically independent gates: a first gate that controls a first plurality of cells and a second gate that controls a second plurality of cells. This segmentation allows independent control of different cell groups, enabling over-voltage protection functionality without requiring complete redesign of the entire device architecture.
2Strength
If the semiconductor device uses wide bandgap material like gallium nitride for higher voltage tolerance, then the device can handle higher voltages, but the device lacks intrinsic body diode and avalanche capability, making it more susceptible to destructive voltage increases
Solution Approach 1:
The second gate acts as an intermediary control mechanism that can independently manage a portion of the cells. During UIS events, this gate can be activated to provide alternative current paths or control mechanisms, compensating for the lack of intrinsic body diode and avalanche capability in wide bandgap materials.
3Adaptability or versatility
If the semiconductor device operates under unclamped inductive switching conditions, then the device can handle inductive loads, but the stored magnetic energy induces high potentials that exceed the rated breakdown voltage and cause catastrophic failure
Solution Approach 1:
The device is designed with dual gate control capability before UIS events occur. The control circuitry can detect upcoming UIS conditions and activate the second gate in advance to prepare protective mechanisms, such as creating alternative current paths or adjusting cell conductivity, thereby preventing catastrophic voltage breakdown before it occurs.
Data Source
AI summary
Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.