Independent Link and Bank Selection for Memory Signal Integrity
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Solution Overview
Problem
Current memory devices face limitations in high-speed operations due to signal quality issues at high frequencies, leading to communication degrading effects like cross-talk and signal attenuation, which restricts their use in future electronic devices requiring high data rates, such as mobile multimedia devices recording high-definition moving pictures.
Innovation Solution
A memory system with multiple memory banks and links that employs switching logic to prevent simultaneous or overlapping access attempts, ensuring valid access by controlling the operation of link controllers and memory banks, thereby maintaining signal quality and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel interface is used for high-speed memory operation, then data transfer rate is improved, but signal quality deteriorates due to cross-talk and signal attenuation
Solution Approach 1:
The patent segments the parallel interface into multiple independent serial links, each operating at lower frequency but collectively providing high data transfer rates. This segmentation allows each link to maintain signal integrity while the aggregate system achieves high throughput through parallel serial connections.
Solution Approach 2:
The patent introduces link controllers as intermediary devices that manage data transmission between the memory system and external devices. These controllers serialize/deserialize data streams and handle protocol management, enabling high-speed communication while maintaining signal quality through controlled serialization.
2Productivity
If multiple links access multiple banks simultaneously, then productivity is improved, but access conflicts occur leading to invalid operations
Solution Approach 1:
The patent implements feedback mechanisms through link controllers that monitor and coordinate access requests from multiple links to multiple banks. The controllers receive feedback about current bank access states and adjust their transmission timing accordingly, preventing conflicts while maintaining high throughput through coordinated parallel access.
Solution Approach 2:
The patent employs dynamic access control where link controllers can adaptively adjust timing and prioritize access requests based on current system state. This dynamic coordination allows flexible handling of multiple simultaneous access requests while preventing invalid operations through real-time conflict detection and resolution.
Data Source
AI summary
Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.