Independent Microcontrollers Eliminate Switch Matrix Latency
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Solution Overview
Problem
Existing multi-core microcontroller devices face performance and reliability issues due to shared system resources, latency, and vulnerability to failures, particularly with crossbar switches and switch matrices, which add complexity and cost.
Innovation Solution
A microcontroller device comprising two independent microcontrollers with dedicated interfaces, such as a bidirectional mailbox and unidirectional master-slave interfaces, sharing external pins while each having its own memory and peripherals, allowing for flexible pin assignment and power control, thereby avoiding the need for switch matrices and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If switch matrices are used to allow multiple processors to access shared system resources, then resource sharing capability is improved, but latency increases and reliability deteriorates due to conflict resolution circuitry and single point of failure
Solution Approach 1:
The patent divides the system into multiple independent microcontroller units, each with its own dedicated system resources (buses, memories, peripherals). This segmentation eliminates the need for shared resources and switch matrices, thereby removing the single point of failure and conflict resolution latency while maintaining resource accessibility for each unit.
2Adaptability or versatility
If crossbar switches are used to link microcontroller core to peripherals, then resource access flexibility is improved, but latency increases and vulnerability to failure worsens
Solution Approach 1:
Each microcontroller unit has dedicated system buses directly connecting its CPU to its own peripherals and memory resources. This eliminates the need for crossbar switches and intermediate routing, providing direct access paths that reduce latency while maintaining flexibility through independent configuration of each unit's connections.
3Reliability
If multiple switch matrices are implemented for fault resolution, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The system uses multiple independent microcontroller units, each with its own dedicated resources. This architectural segmentation provides inherent fault isolation - if one unit fails, others continue operating independently - without requiring additional switch matrices or complex fault resolution circuitry, thereby maintaining reliability while reducing complexity.
4Productivity
If shared peripherals are used in multi-core devices, then resource utilization is improved, but conflict resolution latency increases
Solution Approach 1:
The patent assigns dedicated peripherals to each microcontroller unit, eliminating shared resource conflicts. Each unit can access its assigned peripherals immediately without waiting for conflict resolution, thereby maintaining high resource utilization while avoiding latency associated with shared resource arbitration.
Data Source
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AI summary
A microcontroller device has a housing with a plurality of external pins. a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.