Technology Database Independent Pcells for IC Package Design

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Solution Overview

Problem

Conventional EDA tools require manual adaptation and maintenance of unique library cells for each routing layer in IC package design, making it cumbersome and inefficient, especially when dealing with complex ICs and unknown future layers.

Innovation Solution

Implementing technology database independent pcells that can automatically retrieve necessary information from a parent cell's technology database to configure their geometry, allowing seamless transition between schematic and layout views without requiring manual input for each layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional EDA tools are used to design IC packages, then circuit functionality can be achieved, but manual adaptation and maintenance of unique library cells for each routing layer becomes cumbersome and inefficient

Engineering Contradiction:
Improvepackage design efficiencyVSAvoidlibrary cell management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a universal pcell library that can be used across multiple routing layers and technology nodes without requiring separate library cells for each layer. The pcells are designed to automatically adapt to different layer configurations, eliminating the need for manual library adaptation and maintenance for each routing layer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The pcells are equipped with self-configuration capabilities that automatically retrieve technology database information and adjust their geometry parameters without manual intervention. This self-service mechanism eliminates the cumbersome manual adaptation process required by conventional EDA tools.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If unique library cells are created for each routing layer, then layer-specific geometry requirements are met, but the process of adapting pcells becomes cumbersome and inefficient

Engineering Contradiction:
Improvelayer-specific geometry accuracyVSAvoidpcell adaptation effort
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The pcells are designed with dynamic parameters that can automatically adjust their geometry based on the routing layer they are placed on. Instead of creating static library cells for each layer, the pcells dynamically retrieve layer-specific information from the technology database and configure themselves accordingly, maintaining manufacturing precision while eliminating manual adaptation effort.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent utilizes parameter changes in the pcells to adapt to different routing layers. The pcells automatically modify their geometric parameters based on the technology database information retrieved for each specific layer, ensuring layer-specific geometry accuracy without requiring manual creation of unique library cells for each layer.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If pcells are supplied by EDA vendors, then basic functionality is provided, but they require manual adaptation to represent multiple routing layers for a particular technology

Engineering Contradiction:
Improvetechnology-specific customizationVSAvoidmanual editing requirement
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The pcells are enhanced with self-service capabilities that automatically retrieve technology database information and configure themselves for the specific technology and routing layers being used. This eliminates the need for manual editing while maintaining full adaptability to different technology nodes and layer configurations.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The pcells implement a feedback mechanism where they automatically query the technology database for layer-specific information and adjust their configuration accordingly. This feedback loop enables the pcells to adapt to multiple routing layers without manual intervention, combining ease of operation with technology-specific customization.

Inventive Principle:
Principle #23Feedback

4Loss of information

If layout footprint of discrete components is captured prior to package assembly, then component placement is determined, but the package designer loses knowledge of which layers the components will reside in

Engineering Contradiction:
Improvelayer assignment informationVSAvoiddesign iteration time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The pcells are pre-configured with the capability to automatically retrieve layer information from the technology database during the design process. This preliminary action ensures that layer assignment information is preserved and automatically applied, eliminating the need for time-consuming design iterations to determine component layer placements.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10423750B1Technology database independent components for integrated circuit package
Publication Date: 2019.09.24 CADENCE DESIGN SYST INC
  • US10423750B1 patent drawing
  • US10423750B1 patent drawing
  • US10423750B1 patent drawing

AI summary

Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of the package library of the parent cells to retrieve the layer name, layer number, the design resolution, and/or other information such as design rule information of the parent cells hosting the pcells. Based on the layer number, the resolution, and/or other information the pcells can configure for themselves correct layout geometry without any input from a circuit designer.