Independent Plane Access in Multi-Plane Memory Devices

Solution Overview

Problem

In multi-plane memory devices, the restriction on which planes can be accessed in parallel due to limited independent plane driver circuits leads to increased latency, reduced read input/output operations per second (RIOPS), and decreased quality of service for host systems.

Innovation Solution

Implementing a plane selection circuit that selectively couples memory planes to independent plane driver circuits, allowing any plane to be accessed concurrently without group-based limitations, using multiplexer circuits controlled by control logic to route signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If plane driver circuits are shared among multiple planes, then device complexity is reduced, but parallel access capability is limited and latency increases

Engineering Contradiction:

Improvenumber of driver circuitsVSAvoidaccess latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The memory device is divided into multiple independent plane groups, where each plane group is associated with a dedicated plane driver circuit. This segmentation allows each driver circuit to independently control its associated plane(s), enabling parallel access operations across different planes without sharing constraints, thereby reducing latency while maintaining manageable device complexity through structured organization

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a plane group dimension that organizes planes into dedicated groups, each with its own driver circuit. This dimensional reorganization transforms the access architecture from a shared resource model to a dedicated resource model, allowing simultaneous independent access to multiple planes through multiple driver circuits without increasing overall device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If plane driver circuits are shared among multiple planes, then manufacturing cost is reduced, but read input/output operations per second decreases

Engineering Contradiction:

Improvemanufacturing costVSAvoidRIOPS

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The memory device is divided into multiple independent plane groups, where each plane group is associated with a dedicated plane driver circuit. This segmentation allows each driver circuit to independently control its associated plane(s), enabling parallel access operations across different planes without sharing constraints, thereby reducing latency while maintaining manageable device complexity through structured organization

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a plane group dimension that organizes planes into dedicated groups, each with its own driver circuit. This dimensional reorganization transforms the access architecture from a shared resource model to a dedicated resource model, allowing simultaneous independent access to multiple planes through multiple driver circuits without increasing overall device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Loss of time

If additional independent plane driver circuits are added to access all planes in parallel, then access latency is reduced, but device complexity and circuit area increase

Engineering Contradiction:

Improveaccess latencyVSAvoidnumber of driver circuits

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Each plane driver circuit is designed to serve multiple planes within its associated plane group, making it a universal driver that can access any plane in its group. This multi-functionality allows a single driver circuit to manage multiple planes, reducing the total number of driver circuits needed while still enabling parallel access to all planes, thus avoiding the complexity increase that would result from adding separate dedicated drivers for each plane

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11726690B2Independent parallel plane access in a multi-plane memory device

Publication Date: 2023.08.15 MICRON TECHNOLOGY INC

AI summary

A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.