Indexable Insert Ridges for Chip Control and Durability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing indexable inserts for turning suffer from early deterioration of chip processability due to high load and abrasion at breaker projection regions, especially at high cutting speeds or large feeds, leading to crater abrasion and reduced durability.
Innovation Solution
A polygonal indexable insert with a nose cutting-edge and linear cutting edge, featuring a first ridge and second ridges that are symmetrically disposed, where the second ridges are convex-curved and lower in height, providing a flat breaker base and increasing the contact area to alleviate load and enhance protection, guiding chips during large-depth cutting to reduce direct impact on the first ridge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length between the cutting edge and the breaker projection is increased to reduce load and temperature, then crater abrasion and coating detachment are reduced, but chip processability deteriorates
Solution Approach 1:
The breaker projection is divided into two distinct parts: a first breaker projection extending from the boss surface toward the nose, and second breaker projections extending from the first breaker projection to the slope. This segmentation allows each part to perform different functions - the first breaker projection maintains structural support while the second breaker projections handle chip breaking, thereby reducing load on individual components while preserving chip processability
Solution Approach 2:
The breaker projections are designed with specific geometric dimensions and orientations - the first breaker projection has a predetermined length from the boss surface, and the second breaker projections have controlled lengths and orientations relative to the linear cutting edge. This dimensional optimization allows the breaker projections to effectively break chips while distributing mechanical loads across multiple surfaces, preventing both chip processability deterioration and excessive wear
2Productivity
If breaker projections are provided near the noses for large-depth cutting, then chip clogging is prevented, but the pressing force causes rapid abrasion at section B
Solution Approach 1:
The second breaker projections are designed with varying dimensions and orientations at different locations. Specifically, the second breaker projections have different lengths and angles relative to the linear cutting edge, allowing each local region to optimize chip breaking while distributing pressing forces. This local quality variation prevents concentration of stress at any single point, thereby reducing rapid abrasion while maintaining effective chip processability
3Productivity
If the first breaker projection and rising surface extend from midsection of slope, then chip curling is achieved, but point contact causes intensive abrasion and cutting edge chipping
Solution Approach 1:
The first breaker projection is designed with a curved upper surface that is convex toward the nose and concave toward the boss surface. This curvature creates a broader contact area with the chip during breaking, replacing point contact with surface contact. The curved geometry allows the chip to ride along the convex surface while being broken by the concave region, distributing mechanical stresses and preventing intensive abrasion and cutting edge chipping while maintaining effective chip curling
Data Source
AI summary
An indexable insert has a rake face on which a first ridge (2) and a second ridge (3) are provided. The first ridge (2) protrudes from a boss surface (1) towards a nose, and the second ridge (3) extends continuously from the first ridge (2) to a slope (8) connected to a cutting-edge land (7) of a linear cutting edge (6). The second ridge (3) has a height lower than that of the first ridge (2) and is convex-curved towards a bisecting line (CL) of an apex angle of the nose in plan view, thereby achieving both enhanced chip processability and reduction of load received when raking a chip.