Indexed Delay Circuits for Synchronous Signal Distribution in IC Blocks
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Solution Overview
Problem
In large semiconductor integrated circuits, digital signals applied to identical blocks through conductive lines experience delays due to the length of the lines, leading to synchronization issues, where the signal may not arrive in the same clock period across all blocks, particularly in circuits with 8 to 10 consecutive identical blocks.
Innovation Solution
A timing circuit is introduced that adjusts the signal delay for each block based on its position in the sequence, using an index signal propagated through the blocks to select the appropriate delay duration, ensuring all blocks receive the signal simultaneously by adding a modular delay that compensates for the intrinsic delay of the conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single conductive line distributes a digital signal to N identical blocks along a rectangular axis, then the circuit layout is simple and manufacturing is easier, but the signal arrives at different times at each block due to the time constant and length of the conductive line, causing synchronization issues
Solution Approach 1:
The conductive line is divided into N segments, with each segment serving a specific block. Each segment has its own delay circuit, allowing independent timing adjustment for each block while maintaining the overall simple linear layout structure
Solution Approach 2:
Delay circuits are incorporated at each block's input to pre-adjust the signal timing before it reaches the block's internal logic. This preliminary timing adjustment ensures that all blocks receive synchronized signals despite the varying distances from the signal source
2Manufacturing precision
If delay circuits are added to each block to synchronize signal arrival, then signal synchronization is achieved, but the device complexity increases due to additional circuits in each block
Solution Approach 1:
The delay amount is adjusted as a variable parameter based on the block's position in the sequence. Blocks farther from the signal source receive larger delay adjustments, while closer blocks receive smaller delays, optimizing synchronization without uniform complexity across all blocks
Solution Approach 2:
A standardized delay circuit module is designed and replicated N times, once for each block. This copying approach simplifies the overall design process and reduces the burden of creating unique complex circuits for each block while achieving the required synchronization
3Productivity
If the circuit is divided into N identical elementary blocks for mask-matching lithography production, then manufacturing efficiency is improved and production cost is reduced, but the signal distribution time varies across blocks due to their positions
Solution Approach 1:
The delay compensation is built into each block's design during the manufacturing phase. This preliminary incorporation of delay circuits ensures that signal synchronization is achieved without requiring post-manufacturing adjustments, maintaining high manufacturing efficiency
Solution Approach 2:
The same standardized delay circuit module serves multiple functions: it provides signal delay adjustment, maintains signal integrity, and ensures synchronization across all N identical blocks, reducing the need for separate compensation mechanisms
Data Source
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AI summary
The invention proposes a method for distributing a signal over each block Bj of a series of N adjacent blocks of identical design of an electronic circuit. It proposes, in an identical manner for each of the N blocks, placing a time delay circuit MUX-DELj on the path conveying a signal Sc from the input INcj of the block to an internal electrical node Ndj of the block for said signal Sc; arranging for the time delay circuit to supply N delayed signals corresponding to N different time delays Δf1,... Δfj,...ΔfN separated by an elementary time increment Δt that corresponds to the elementary delay Δt for traversing a block introduced into a conductive line; and selecting the delayed signal corresponding to the time delay applicable in accordance with the block in question, by means of an index signal propagated through the N blocks, and that increments or decrements on passing through each block.