Indexed Conditional Jump Processor for Shorter RISC Branch Code
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Solution Overview
Problem
The existing RISC processors face inefficiencies due to the large number of steps required for conditional jump subroutines, particularly in indirect addressing, which leads to increased processing time and resource utilization.
Innovation Solution
A processor architecture that executes a conditional jump instruction using a single instruction that quotes an index register, storing jump-destination effective addresses or offsets into multiple reference registers, and sets the program counter with a single step to achieve the jump-destination address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional RISC processors use multiple steps for conditional jump subroutines with indirect addressing, then the processor can execute complex control flow, but the number of instructions increases and processing time increases
Solution Approach 1:
The patent merges multiple separate instructions (auipc, addi, branch) into a single conditional jump instruction that performs all address calculation and branching in one operation. This combines the functions of program counter loading, address offset calculation, and conditional branching that were previously separate steps, thereby reducing instruction count and improving processing speed while maintaining control flow capability.
Solution Approach 2:
The conditional jump instruction is designed to perform multiple functions simultaneously: it loads the program counter, calculates the effective address by adding offset to base address, and executes the branch decision all in one instruction. This multi-functional design eliminates the need for separate instructions for each operation, resolving the contradiction between versatility and productivity.
2Adaptability or versatility
If conventional RISC processors use multiple instructions for indirect addressing, then the processor can achieve flexible address calculation, but the assembly code length increases
Solution Approach 1:
The patent combines multiple instructions (auipc for program counter loading, addi for address offset calculation, and branch for conditional jumping) into a single conditional jump instruction. This merging reduces the total number of instructions and shortens assembly code length while preserving the flexibility to calculate various addresses through the base address and offset parameters.
3Adaptability or versatility
If RISC processors execute conditional jump subroutines with multiple steps, then the processor can implement indirect addressing, but the number of processing steps increases
Solution Approach 1:
The patent segments the address calculation into components (base address from register, offset from immediate value) that can be combined in a single instruction. This segmentation allows the processor to maintain indirect addressing capability while reducing the number of processing steps from multiple sequential operations to a single integrated operation, thereby reducing processing time.
Solution Approach 2:
The base address is loaded into a register before the conditional jump instruction is executed. This preliminary action prepares the address calculation components in advance, allowing the single conditional jump instruction to complete the entire address calculation and branching operation without requiring multiple sequential steps, thus reducing processing time.
Data Source
AI summary
Provided is a processor enabling assembly code of a direct-addressing conditional-jump subroutine to be reduced. The processor includes a logic circuit executing a conditional-jump instruction of assembly code, and logically configured to: store, into an index register, an index register number that is an index to a jump-destination effective address; store jump-destination effective addresses differing from one another, or address offsets to jump-destination effective addresses differing from one another, into plural reference registers, respectively; fetch and decode a conditional jump instruction that is one instruction that quotes the index register; and then execute (S1) acquiring a jump-destination effective address or an address offset from the reference register corresponding to the index register number of the content of the index register and (S2) setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the address offset, to a register serving as the program counter.