Indexed Load Instructions for Non-Contiguous Memory Access
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Solution Overview
Problem
Current processors face inefficiencies in memory access, particularly in loading data from non-contiguous memory locations, which affects performance in memory-intensive applications such as sparse matrix processing and big data computations.
Innovation Solution
The introduction of indexed load instructions that allow for the specification of packed memory address information and additional address generation, enabling the processor to load multiple data elements from non-contiguous memory locations directly into a destination storage location, bypassing caches to reduce cache pollution and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is loaded from non-contiguous memory locations using traditional methods, then data can be accessed, but cache pollution increases and memory access efficiency decreases
Solution Approach 1:
The patent segments the memory address generation process by introducing indexed load instructions that separately handle base addresses, indices, and strides. This allows selective caching of only the necessary address components rather than loading entire cache lines, thereby reducing cache pollution while maintaining access to non-contiguous memory locations.
Solution Approach 2:
The patent applies local quality by enabling different caching strategies for different portions of memory access operations. Specifically, it allows indices and base addresses to be cached separately from data elements, and enables non-temporal loads that bypass caches for specific memory regions while using caches for others, optimizing the local caching behavior based on access patterns.
2Productivity
If traditional load instructions are used to access scattered memory locations, then data loading is possible, but resource usage increases and performance deteriorates
Solution Approach 1:
The patent merges multiple traditional load instructions into a single indexed load instruction that can simultaneously access multiple scattered memory locations. By combining base address, index, and stride into one instruction, it reduces the number of instructions and resources required compared to executing multiple separate load operations.
Solution Approach 2:
The indexed load instruction provides multi-functionality by handling both contiguous and non-contiguous memory access patterns through a single unified instruction. It can operate with stride values of zero for contiguous access or non-zero for scattered access, eliminating the need for separate instruction sequences and reducing resource consumption.
3Productivity
If multiple data elements are loaded from scattered memory locations, then data can be gathered, but the process becomes complex and power consumption increases
Solution Approach 1:
The patent performs preliminary action by pre-calculating and caching the base address and stride values before executing the indexed load operation. This allows the actual data gathering to use simple index addition rather than complex address calculation during execution, reducing both operational complexity and power consumption.
Solution Approach 2:
The patent changes parameters by introducing stride as a configurable parameter that determines the access pattern. By varying the stride parameter, the same indexed load instruction can efficiently handle both contiguous memory access (stride=0) and scattered memory access (stride>0), optimizing power consumption based on the specific access pattern required.
Data Source
AI summary
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.