Indexing External Memory in Reconfigurable Compute Fabric

The patent segments memory into multiple banks (first bank, second bank, etc.) that can be accessed independently and simultaneously. Each compute element can access different memory banks in parallel, reducing the time penalty of large memory capacity while maintaining high data availability through spatial segmentation of the memory space.

The patent introduces a new dimension of parallelism by organizing memory access across multiple compute elements that can simultaneously access different memory locations. Instead of sequential access through a single bus, the system uses a mesh network topology where multiple data paths exist concurrently, transforming the access model from one-dimensional sequential to multi-dimensional parallel access.

The patent merges computation and memory access functions into an integrated architecture where compute elements are directly coupled to memory banks through a mesh network. This combination eliminates the need for separate data movement operations between distinct processor and memory units, reducing energy consumption while maintaining high computational capacity through tight integration of storage and processing functions.

Each compute element can independently access memory banks without requiring centralized data movement control. The distributed architecture allows compute elements to self-service their data needs directly from local and remote memory banks through the mesh network, eliminating energy-intensive centralized data shuffling and reducing overall system energy consumption.

The patent implements a dynamically reconfigurable mesh network that can adapt its connectivity and data flow patterns based on computational requirements. The system transitions from the static, fixed data path of conventional Von Neumann architecture to a dynamic topology where compute elements and memory banks can communicate through multiple adaptable paths, enabling high performance while maintaining manageable complexity through systematic design.

The mesh network architecture provides universal connectivity where any compute element can access any memory bank through multiple possible paths. This multi-functional communication infrastructure replaces the specialized, single-purpose data bus of conventional architectures, delivering superior performance while maintaining system simplicity through a unified, scalable interconnection topology that handles diverse computational workloads.