Indirect Branch Synchronization via Precomputed Target Tables
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Solution Overview
Problem
Current control flow monitoring methods, particularly those using disjoint signatures, struggle to manage indirect branching instructions effectively due to synchronization challenges and memory costs, especially when dealing with multiple target addresses, which are either predictable or unpredictable.
Innovation Solution
The generation of program codes that include synchronization information within the main program code to allow the auxiliary processing unit to synchronize with the main processing unit during indirect branch executions, eliminating the need for additional memory and enabling management of multiple target addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If indirect branch instructions are used in the monitored program, then code size is reduced and cycle penalties are minimized, but the coprocessor cannot properly synchronize with the processor because the target address cannot be determined from the instruction alone
Solution Approach 1:
The patent pre-calculates and stores all possible target addresses of indirect branch instructions in a lookup table during program analysis phase. Before execution, the coprocessor is provided with this pre-computed target address information, allowing it to synchronize properly with the processor even when the actual target is determined at runtime. This preliminary preparation resolves the synchronization problem without requiring changes to the indirect branch mechanism itself.
Solution Approach 2:
The patent introduces an intermediary data structure (target address table) that mediates between the indirect branch instruction and the coprocessor's branch instruction. This table stores the mapping between indirect branch instructions and their possible target addresses, allowing the coprocessor to determine the correct target address by looking it up in the table rather than trying to calculate it directly from the instruction. This intermediary resolves the information asymmetry between processor and coprocessor.
2Adaptability or versatility
If multiple target addresses are supported for indirect branches, then the ability to handle complex control flow is improved, but the encoding capacity of branch instructions is insufficient to store multiple addresses
Solution Approach 1:
The patent moves the storage of multiple target addresses from the instruction encoding dimension to a separate data dimension (lookup table in memory). Instead of trying to encode multiple addresses within the limited instruction format, the system uses an external data structure to store the address mappings. This dimensional shift allows support for multiple targets without increasing instruction complexity.
Solution Approach 2:
The patent creates a copy of the target address information in a lookup table that the coprocessor can access. Rather than requiring the original instruction to contain all possible target addresses, the system copies the necessary target address mappings into a separate data structure that both processor and coprocessor can reference. This copying approach enables multi-target support while keeping instructions compact.
3Adaptability or versatility
If a lookup table is used to store multiple target addresses, then multiple targets can be managed, but additional memory is required which increases memory cost
Solution Approach 1:
The patent makes the lookup table serve multiple functions: it stores target address mappings for synchronization, provides control flow information for verification, and enables the coprocessor to handle indirect branches. By making this data structure multi-functional, the patent reduces the need for separate specialized memory structures, thereby optimizing memory usage while maintaining full functionality for multi-target indirect branch support.
4Productivity
If the coprocessor autonomously accesses memory to maintain synchronization, then system performance is not degraded, but memory access overhead increases
Solution Approach 1:
The patent pre-loads and caches the target address information in the lookup table during program analysis or initialization, so that during execution the coprocessor can quickly retrieve address mappings without requiring complex real-time calculations or frequent memory accesses. This preliminary preparation reduces the time penalty of autonomous memory access during critical execution paths.
Data Source
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AI summary
Synchronization points (@WD_ti) are inserted into the program code to be controlled, which are associated with the different branches resulting from the execution of an indirect branch instruction (INSPF4). These synchronization points are accessible by the control program code in order to identify which branch to use when executing the indirect branch instruction (INSXF4) of the control program code.