Indirect Memory Prefetch Pipeline Using Shifted Cacheline Offsets

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Solution Overview

Problem

Indirect memory prefetchers face inaccuracies and latency issues in predicting memory access patterns for complex tasks, leading to pipeline stalls and reduced performance.

Innovation Solution

A method is proposed to compute a precise offset of the trigger virtual address relative to the cacheline start, using a logically shifted version of the distance parameter and stride size to generate an accurate prefetch address and vector structure, preventing pipeline stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional indirect memory prefetcher methods are used, then the system can handle complex memory access patterns, but pipeline stalls occur and performance is reduced

Engineering Contradiction:

Improveprefetch accuracyVSAvoidpipeline stall latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by computing the offset of the trigger virtual address relative to the cacheline start using a logically shifted version of the distance parameter before the actual prefetch operation. This advance computation of the prefetch address and vector structure prevents pipeline stalls by ensuring all address calculation is completed prior to data fetching, thereby improving prefetch accuracy without incurring latency during the prefetch execution phase

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If precise prefetch address computation is performed, then prefetch accuracy improves, but computation complexity increases

Engineering Contradiction:

Improveprefetch address precisionVSAvoidaddress computation complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical division operations with a logically shifted version of the distance parameter. Instead of performing full division to compute the offset of the trigger virtual address relative to the cacheline start, the invention uses bit shifting operations which are simpler and faster to execute, thereby maintaining prefetch address precision while reducing computation complexity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the parameter representation by using a logically shifted version of the distance parameter instead of the raw distance value. This parameter transformation enables precise offset computation through simpler logical operations, achieving high prefetch address precision without the computational overhead of traditional methods

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12517831B1Efficient non-stalling cacheline triggered prefetch pipeline optimization for indirect memory accesses

Publication Date: 2026.01.06 QUALCOMM INC

AI summary

Certain aspects provide a method of efficiently computing a starting address and offset for a memory prefetch address. The method generally includes computing a distance parameter that represents a difference between a line trigger virtual address and a producer virtual address, generating a starting address for a memory prefetch as a function of the distance parameter and a stride size, wherein the staring address is generated using a logically shifted version of the distance parameter if a first condition is met, and performing the memory prefetch using the generated starting address.