Indirect Memory Prefetch Pipeline for Non-Stalling Cacheline Triggers

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Solution Overview

Problem

Indirect memory prefetchers face inaccuracies and latency issues in predicting memory access patterns for complex tasks, leading to pipeline stalls and reduced performance.

Innovation Solution

A method is proposed to compute a precise offset of the trigger virtual address relative to the cacheline start, using a logically shifted version of the distance parameter and stride size to generate an accurate prefetch address and vector structure, preventing pipeline stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional indirect memory prefetchers are used to handle complex memory access patterns, then the system can support sophisticated workloads, but pipeline stalls occur and performance decreases

Engineering Contradiction:

Improveability to handle complex memory access patternsVSAvoidpipeline throughput

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs preliminary actions by computing the offset of the trigger virtual address relative to the cacheline start before initiating the prefetch pipeline. This pre-computation ensures that the prefetch address calculation is ready in advance, preventing pipeline stalls and maintaining continuous data flow through the system

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If precise prefetch address calculation is implemented to improve prefetch accuracy, then cache misses are reduced, but the computational complexity increases

Engineering Contradiction:

Improveprefetch address accuracyVSAvoidaddress calculation complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation by using the offset of the trigger virtual address relative to the cacheline start as a key parameter. This parameter transformation simplifies the address calculation process while maintaining precise prefetch accuracy, as the offset can be easily combined with the cacheline base address to generate accurate prefetch addresses

Inventive Principle:

Principle #35Parameter changes

3Productivity

If the prefetch pipeline operates continuously without optimization, then data fetch operations are performed, but latency issues arise and prefetch timeliness decreases

Engineering Contradiction:

Improveprefetch operation throughputVSAvoidprefetch latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies the skipping principle by directly computing the prefetch address using the pre-calculated offset and cacheline base address, bypassing intermediate computation steps. This direct calculation approach rushes through the address generation process, minimizing latency and ensuring timely prefetch operations

Inventive Principle:

Principle #21Skipping (Rushing through)

Data Source

PatentUS20260072844A1Efficient non-stalling cacheline triggered prefetch pipeline optimization for indirect memory accesses

Publication Date: 2026.03.12 QUALCOMM INC

AI summary

Certain aspects provide a method of efficiently computing a starting address and offset for a memory prefetch address. The method generally includes computing a distance parameter that represents a difference between a line trigger virtual address and a producer virtual address, generating a starting address for a memory prefetch as a function of the distance parameter and a stride size, wherein the staring address is generated using a logically shifted version of the distance parameter if a first condition is met, and performing the memory prefetch using the generated starting address.