Indirect Prefetch Training Filter for Producer Load Selection

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Solution Overview

Problem

Existing software compilers complicate indirect prefetch training by causing unexpected behavior in producer-consumer relationships, leading to increased difficulty in identifying producer loads and resulting in missed consumer loads, which reduces the accuracy of prefetching and increases memory access latency.

Innovation Solution

Implement access tracking storage circuitry to store memory access requests and indirect prefetch training filtering circuitry to select memory access requests for training based on comparing access information, ensuring the first iteration of a producer load is selected and subsequent iterations are excluded, thereby improving the accuracy of prefetch training.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If existing software compilers are used to generate producer-consumer relationships, then code generation is simplified, but indirect prefetch training accuracy deteriorates due to unexpected behavior and difficulty in identifying producer loads

Engineering Contradiction:
Improvecode generation simplicityVSAvoidprefetch training accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary filtering circuit between the compiler-generated code and the prefetch training mechanism. This filtering circuit analyzes memory access patterns and identifies true producer-consumer relationships by examining address dependencies, thereby mediating between the simplified compiler output and the accurate prefetch training requirements without requiring compiler changes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If all memory access requests are selected for indirect prefetcher training, then training coverage is increased, but training accuracy deteriorates due to inclusion of redundant or incorrect producer-consumer relationships

Engineering Contradiction:
Improvetraining data volumeVSAvoidprefetch training accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The filtering circuit extracts only the relevant and correct producer-consumer relationships from the stream of memory access requests by analyzing address dependencies and identifying true producers. This extraction process removes redundant or incorrect relationships while preserving the essential training data, achieving both quality and efficiency in prefetch training

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If producer-consumer relationships with variable data values are tracked, then prefetching flexibility is improved, but training difficulty increases due to variability in access patterns

Engineering Contradiction:
Improveprefetching flexibilityVSAvoidtraining difficulty
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The filtering circuit monitors changes in address parameters and data values to identify when variable-based indirect prefetching opportunities arise. By tracking parameter variations and recognizing patterns despite variability, the system maintains prefetching flexibility while managing training complexity through adaptive parameter analysis rather than rigid pattern matching

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260044345A1Indirect prefetcher training
Publication Date: 2026.02.12 ARM LTD
  • US20260044345A1 patent drawing
  • US20260044345A1 patent drawing
  • US20260044345A1 patent drawing

AI summary

An apparatus includes access tracking storage circuitry configured to store access entries indicative of recently performed memory access requests; and indirect prefetch training filtering circuitry configured to receive a memory access request, and to determine whether to select the received memory access request for indirect prefetcher training based on comparing access information associated with the received memory access request to the access entries indicative of recently performed memory access requests.