Indirect Register Data Access via Address Bus
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Solution Overview
Problem
Current memory subsystems lack efficient mechanisms to access data stored in register devices connected to the address or command bus without requiring additional hardware or resulting in slow connections, especially in systems that perform parity error checking, which can lead to system failures.
Innovation Solution
A mechanism that allows indirect reading of register data via the address or command bus, enabling data transfer to a memory device connected to both buses, allowing host processors to access register contents during normal operation and facilitating error recovery by isolating and logging parity errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a connection to the data bus is included to access register data, then data accessibility is improved, but hardware cost and routing complexity increase significantly
Solution Approach 1:
The address bus is made multi-functional by enabling it to carry both address information and data information. The register device can place data onto the address bus when triggered by a read command, allowing the same bus to serve dual purposes for both addressing and data transfer, thereby eliminating the need for separate data bus connections to registers.
Solution Approach 2:
The memory device acts as an intermediary between the register device and the host processor. When the host processor issues a read command to a register, the memory device facilitates the transfer of data from the register onto the address bus and makes it available on the data bus, enabling indirect access without direct register-to-data-bus connectivity.
2Measurement precision
If parity error checking is performed at the register device, then error detection capability is improved, but system reliability decreases due to potential hangs on erroneous commands
Solution Approach 1:
The register device performs preliminary action by checking parity errors on commands before they are sent to the memory device. When a parity error is detected, the register device logs the erroneous command and prevents it from being executed, thereby avoiding system hangs while maintaining error detection capability.
Solution Approach 2:
The harmful effect of parity errors causing system hangs is converted into a beneficial error detection and logging mechanism. By capturing and logging erroneous commands in the register device, the system can identify and prevent harmful operations while maintaining normal operation for valid commands.
3Ease of operation
If an out-of-band serial interface is provided on the register device, then data accessibility is improved, but hardware requirements and routing costs increase
Solution Approach 1:
The address bus is made multi-functional by enabling it to carry both address information and data information. The register device can place data onto the address bus when triggered by a read command, allowing the same bus to serve dual purposes for both addressing and data transfer, thereby eliminating the need for separate data bus connections to registers.
Data Source
AI summary
A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.