Indistinguishable TIE Cells for Semiconductor Chip Reverse Engineering Protection
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Solution Overview
Problem
Reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as attackers can steal and replicate circuit designs, and existing methods to thwart this, such as camouflaged circuits, are often too expensive for mass production.
Innovation Solution
The implementation of indistinguishable TIE cells (ITC-X cells) that use well contacts instead of source or drain diodes to conceal Boolean Secrets, making it difficult for attackers to detect using automated pattern recognition, and are designed to be resistant to Forced Ion Beam attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If camouflaged circuits are used to thwart reverse engineering, then security against reverse engineering is improved, but manufacturing cost increases
Solution Approach 1:
The circuit is divided into functional segments (TIE cells) that can be independently configured. Each cell contains gate-insulator-semiconductor structures that can be selectively activated or deactivated through doping variations, allowing security features to be segmented and distributed throughout the circuit without requiring complete circuit redesign
Solution Approach 2:
Different regions of the circuit are assigned different properties through selective doping. The gate-insulator-semiconductor structures have locally varied doping concentrations that create distinct electrical characteristics in specific areas, enabling automated pattern recognition to identify these localized variations as security features rather than uniform circuit elements
2Difficulty of detecting and measuring
If indistinguishable TIE cells with well contacts are used, then detection difficulty for attackers is improved, but circuit complexity increases
Solution Approach 1:
The gate-insulator-semiconductor structures serve multiple functions: they act as standard circuit elements for normal operation while simultaneously serving as detectable markers for security verification. The same structural elements participate in both circuit functionality and security identification, eliminating the need for separate security circuitry
Solution Approach 2:
The security features are implemented by creating copies of standard circuit elements (TIE cells) with subtle modifications. These copied structures maintain functional equivalence to standard cells while incorporating well contacts and doping variations that enable automated detection, allowing security features to blend into the overall circuit design
3Reliability
If gate-insulator-semiconductor structures with doping variations are used, then resistance to Forced Ion Beam attacks is improved, but manufacturing precision requirements increase
Solution Approach 1:
The security features are implemented by changing doping parameters (concentration, distribution, depth) of the gate-insulator-semiconductor structures. These parameter variations create detectable electrical characteristics while remaining within standard manufacturing process capabilities, avoiding the need for ultra-precise doping that would be difficult to control
Data Source
AI summary
According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.