Indium-Implanted Contact Plug Resistance Reduction
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Solution Overview
Problem
As semiconductor devices downsize and integrate, the TiSi2 layer at the bottom of contact holes is insufficient to prevent increased resistance in contact plugs, and the implantation of indium ions can cause silicon crystal defects due to their larger atom radius.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a contact hole reaching a high-concentration N-type diffusion layer, implantation of indium ions with a specific energy and dose range to grow an indium-containing layer at the contact hole bottom, followed by forming a metal silicide layer and barrier layer to reduce contact plug resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If indium ions are implanted into the whole surface of the N-type diffusion layer, then the contact plug resistance is reduced, but silicon crystal defects are caused due to the larger atom radius of indium
Solution Approach 1:
The patent applies local quality by implanting indium ions selectively at the bottom of contact holes where resistance reduction is most critical, rather than uniformly across the entire diffusion layer surface. This localized approach concentrates the beneficial effect on contact resistance while minimizing the harmful effect of indium accumulation in the bulk silicon crystal lattice.
Solution Approach 2:
The patent segments the indium implantation process into two distinct stages: first forming an initial indium-containing layer at the bottom of contact holes, then performing a second implantation to form a metal silicide layer. This segmentation allows precise control over indium distribution, ensuring high concentration where needed for low resistance while maintaining lower overall concentrations to avoid crystal defects.
2Productivity
If the diameter of the contact hole is reduced for downsizing, then device integration is improved, but the TiSi2 layer at the bottom of the contact hole becomes insufficient to prevent resistance increase
Solution Approach 1:
The patent changes the chemical composition parameter by introducing indium into the TiSi2 layer formation process. Instead of relying solely on titanium silicide, the patent creates an indium-containing layer that forms a metal silicide compound with lower resistance. This parameter change in material composition compensates for the reduced contact hole dimensions and maintains low resistance despite downsizing.
Solution Approach 2:
The patent creates a composite material structure by forming a metal silicide layer comprising titanium silicide and indium silicide compounds. This composite approach combines the barrier properties of titanium silicide with the low resistance characteristics of indium silicide, achieving both low resistance and reliability in miniaturized contact structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a semiconductor device with a contact plug of excellent resistance, reducing the resistance value and minimizing silicon crystal defects by optimizing the indium ion implantation and layer formation.
Implementation Method 1
implanting indium ions of opposite conductivity type to the N-type via the contact hole, in which an implantation amount of the indium ions falls within a range from 1.0×1013/cm2 to 5.0×1014/cm2
Implementation Method 2
a sputtering process is performed to form a titanium layer 4 on the surface of the contact hole 3
Implementation Method 3
annealing treatment is performed in an atmosphere of N2 gas thereby to make the titanium layer 4 become a barrier layer 6 of TiN
Data Source
AI summary
The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×1013/cm2 to 5.0×1014/cm2 to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.