Indium Phosphide Wafer Growth for Low Defect and Low Strain
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Solution Overview
Problem
Conventional semiconductor substrate manufacturing techniques, such as LEC and HB, result in high etch pit density, slip line density, and strain in indium phosphide substrates, leading to reduced yields and increased costs due to defects in electronic and optoelectronic devices.
Innovation Solution
The vertical gradient freeze (VGF) process is employed, which involves a multi-zone heating system to control temperature profiles and crystallization velocity, forming a curved melt/crystal interface, thereby reducing dislocations and slip lines, and resulting in low etch pit density, low slip line density, and low strain indium phosphide substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional LEC or HB processes are used to manufacture indium phosphide substrates, then the manufacturing process is simpler and more established, but the substrates exhibit high etch pit density, high slip line density, and high strain leading to reduced yields
Solution Approach 1:
The patent applies parameter changes by modifying the temperature gradient and cooling rate parameters in the crystal growth process. Specifically, it uses a vertical gradient freeze process with a controlled temperature gradient of 1-8°C/cm and slow cooling rates of 0.1-2°C/hour, which fundamentally changes the crystallization conditions to reduce dislocation density and improve substrate quality
Solution Approach 2:
The patent employs a curved melt/crystal interface instead of a flat interface in the vertical gradient freeze process. This curvature is intentionally designed to reduce stress concentration and dislocation formation during crystallization, directly addressing the high slip line density and strain problems in conventional substrates
2Reliability
If conventional LEC or HB processes are used, then the manufacturing process is more established, but dislocation density and slip line density are high causing wafer breakage and reduced yields
Solution Approach 1:
The patent applies preliminary action by performing a controlled slow cooling process (0.1-2°C/hour) before final substrate formation. This preliminary slow cooling stage allows dislocations to anneal out and the crystal structure to stabilize, preventing wafer breakage during subsequent processing and improving overall manufacturing yield
Solution Approach 2:
The patent implements beforehand cushioning through the vertical gradient freeze process that creates a buffered temperature field with gradient of 1-8°C/cm. This temperature gradient cushioning prevents thermal shock and reduces stress accumulation during crystallization, thereby reducing wafer breakage and improving substrate reliability
3Manufacturing precision
If VGF process with multi-zone heating system is used, then substrate quality improves with low etch pit density and low strain, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the heating system into multiple independent zones along the vertical axis. Each zone can be controlled separately to create the required temperature gradient of 1-8°C/cm, allowing precise control of the melt/crystal interface shape and position while achieving low defect density substrates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VGF process produces indium phosphide substrates with significantly reduced dislocation and slip line densities, enhancing substrate quality and reducing the likelihood of wafer breakage during processing, leading to improved yields and cost efficiency.
Implementation Method 1
starting growth from the partially melted seed by implementing a controlled cooling of the multi-zone heating system
Implementation Method 2
applying a temperature gradient of between 1 and 8 C/cm at a melt-crystal interface
Implementation Method 3
controlling a shape of the interface to be concave to the melt utilizing cooling rates in the multi-zone heating system to form a solidified indium phosphide crystal
Data Source
AI summary
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm−2 or less, or 100 cm−2 or less, or 10 cm−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.