Indium Phosphorus Substrate Surface Roughness Control

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Solution Overview

Problem

Existing methods for producing indium phosphide substrates do not effectively control in-plane surface roughness variations, leading to non-uniform impurity concentration and poor epitaxial film quality, especially for large-diameter substrates.

Innovation Solution

An indium phosphide substrate with controlled surface roughness on both main surfaces, measured using an atomic force microscope, is produced through double-side polishing and single-side finish polishing, ensuring uniformity and reducing impurity concentration, thereby improving epitaxial film quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the compound semiconductor substrate has a large surface area, then the productivity is improved, but the in-plane variations of surface roughness increase leading to non-uniform impurity concentration

Engineering Contradiction:
Improvesemiconductor element production capacityVSAvoidsurface roughness uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention applies different surface roughness control standards to different regions of the substrate. Specifically, the center region (first region) requires Ra ≤ 0.2 nm, while the peripheral region (second region) requires Ra ≤ 0.5 nm. This localized quality approach allows large-diameter substrates to maintain uniform impurity concentration by matching surface roughness characteristics to the specific requirements of each region, thereby enabling high productivity without sacrificing manufacturing precision.

Inventive Principle:
Principle #3Local quality

2Reliability

If the surface roughness is reduced to lower impurity concentration, then the electrical characteristics are stabilized, but the manufacturing complexity increases

Engineering Contradiction:
Improveelectrical characteristics stabilityVSAvoidsubstrate processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention changes the surface roughness parameter to specific ranges (Ra ≤ 0.2 nm for center region, Ra ≤ 0.5 nm for peripheral region) to achieve uniform impurity concentration and stable electrical characteristics. By defining clear numerical parameters for surface roughness control, the invention simplifies the manufacturing process while ensuring reliable electrical performance, avoiding excessive manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If the surface roughness is not controlled, then the manufacturing process is simpler, but the epitaxial film quality deteriorates

Engineering Contradiction:
Improvesubstrate processing simplicityVSAvoidepitaxial film quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The invention applies differentiated surface roughness control to different regions: the center region (first region) requires Ra ≤ 0.2 nm for high-quality epitaxial growth, while the peripheral region (second region) allows Ra ≤ 0.5 nm. This localized approach ensures excellent epitaxial film quality where it matters most while maintaining manufacturing simplicity through relaxed peripheral requirements.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4174913A1Indium phosphorus substrate, indium phosphorus substrate inspection method, and indium phosphorus substrate manufacturing method
Publication Date: 2023.05.03 SUMITOMO ELECTRIC INDUSTRIES LTD
  • EP4174913A1 patent drawingFigure 1~3
  • EP4174913A1 patent drawingFigure 4~5
  • EP4174913A1 patent drawingFigure 6(a)~6(b)

AI summary

An indium phosphide substrate (10) used for an epitaxial wafer which is suitably used for a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT), comprising a first main surface (11) for formation of an epitaxial film of InP thereon and having a surface roughness Ra1 at a center position and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions, the four positions being arranged equidistantly along an outer edge of the first main surface (11) and located at a distance of 5 mm inwardly from the outer edge, wherein an average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 being 0.4 nm or less, and a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 being 10% or less of the average value m1, and a second main surface (12) having a surface roughness Ra6 at a center position and surface roughnesses Ra7, Ra8, Ra9, and RalO at four positions, the four positions being arranged equidistantly along an outer edge of the second main surface (12) and located at a distance of 5 mm inwardly from the outer edge, wherein an average value m2 of the surface roughnesses Ra6, Ra7, Ra8, Ra9, and RalO being 0.2 nm or more and 3 nm or less, and a standard deviation σ2 of the surface roughnesses Ra6, Ra7, Ra8, Ra9, and RalO being 10% or less of the average value m2, wherein the indium phosphide substrate contains a dopant made of Fe.