Induction-Coupled Clock Distribution for IC Skew Reduction

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Solution Overview

Problem

Integrated circuits (ICs) face performance reductions due to the clock skew phenomenon, where clocking signals do not reach all electronic circuits simultaneously, leading to unstable outputs and potential performance failures, especially in larger ICs where significant power consumption and die area are required to manage clock distribution.

Innovation Solution

The implementation of an induction-coupled clock distribution system using inductors or capacitors to inductively and capacitively distribute clocking signals, reducing clock skew by generating magnetic and electrical fields that induce currents and voltages simultaneously across multiple clock reception modules, eliminating the need for numerous buffers and transmission lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional clock distribution paths are used to distribute clocking signals to multiple electronic circuits, then the clocking signal can reach all circuits, but clock skew occurs causing different arrival times and reducing IC performance

Engineering Contradiction:
Improveclock signal synchronizationVSAvoidIC clock frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces the traditional electrical signal transmission through transmission lines and buffers with electromagnetic induction coupling. The clocking signal is converted to a magnetic field by the transmission coil, which then induces current in reception coils at different locations. This substitution of electromagnetic field coupling for electrical signal transmission eliminates the clock skew caused by varying path lengths and buffer delays, allowing simultaneous clock arrival at all circuits while maintaining high clock frequencies.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Area of stationary object

If numerous buffers and transmission lines are added to manage clock distribution in larger ICs, then clock signal can be distributed更广, but power consumption and die area increase significantly

Engineering Contradiction:
Improvedie area for clock distributionVSAvoidpower consumption for clock distribution
Core Design Contradiction:
Area of stationary objectVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and removes the traditional clock distribution infrastructure consisting of numerous buffers and transmission lines from the IC design. By using electromagnetic induction coupling between transmission and reception coils, the system achieves clock signal distribution without requiring these intermediate components. This extraction eliminates the significant die area and power consumption that would be required to support traditional clock distribution in larger ICs, while still enabling widespread clock signal distribution.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If differences in clock distribution path length and number of buffers are reduced, then clock skew is minimized, but device complexity and design difficulty increase

Engineering Contradiction:
Improveclock skew controlVSAvoidclock distribution system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the complex traditional clock distribution system with electromagnetic induction coupling. Instead of carefully matching transmission line lengths and buffer counts to minimize clock skew, the system uses magnetic field coupling where the transmission coil generates a magnetic field that simultaneously induces current in all reception coils regardless of their spatial positions. This substitution fundamentally eliminates the need for complex path length matching and buffer synchronization, greatly reducing design difficulty while maintaining excellent clock skew control.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces clock skew, allows for higher clock frequencies, and decreases power consumption and semiconductor die area usage, enabling more efficient and stable clock signal distribution to multiple electronic circuits within the IC.

Implementation Method 1

A transmission (TX) coil, disposed within the IC clock distribution system, is inductively coupled to a plurality of reception (RX) coils, disposed within the IC clock distribution system

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Implementation Method 2

The master clocking signal causes a magnetic field to emanate from the TX coil. The magnetic field induces a current and/or a voltage onto one or more second clock reception (RX) modules, including a RX coil

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS9501089B2Induction-coupled clock distribution for an integrated circuit
Publication Date: 2016.11.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9501089B2 patent drawing
  • US9501089B2 patent drawing
  • US9501089B2 patent drawing

AI summary

An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.