Inductive Coupling Coil Layout for Stacked Memory Chips
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Solution Overview
Problem
Existing electronic circuits face challenges in downsizing coils for inductive coupling between stacked chips without increasing chip size, which limits communication distance and requires additional metal wiring, compromising memory array reliability.
Innovation Solution
An electronic circuit design that overlaps a metal wiring layer antenna with the memory array region, allowing for a larger coil size and multiple winding configurations to enable long-distance wireless communications without increasing chip size, and uses a transmitter connected to the coil with a potential holding circuit to minimize interference with bit and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a coil is formed by on-chip wiring to enable inductive coupling communications, then wireless communication capability is achieved, but chip size increases due to the large area required for the coil
Solution Approach 1:
The patent utilizes the vertical stacking dimension to resolve the area constraint. By forming coils on separate chips that are then stacked and mounted, the system achieves inductive coupling communications without requiring large horizontal area on a single chip. The coils are disposed in different layers (first chip and second chip), enabling wireless communication while maintaining compact chip footprints.
Solution Approach 2:
The patent divides the coil structure across multiple chips rather than forming a single large coil on one chip. The first coil is formed on a first chip and the second coil is formed on a second chip, with each coil occupying a manageable area. This segmentation allows wireless communication capability to be achieved while keeping individual chip sizes compact.
2Area of stationary object
If the coil area is reduced to minimize chip size, then chip size decreases, but communication distance becomes too short to enable communication with distant chips
Solution Approach 1:
By moving the coil structure to a vertical stacking configuration across multiple chips, the patent extends the effective communication distance without requiring larger coil areas. The stacked arrangement allows for optimized coupling between chips at controlled distances, enabling communication with distant chips while maintaining compact chip sizes.
3Adaptability or versatility
If a coil is disposed in the peripheral circuit region by providing exclusive metal wiring, then wireless communication is enabled, but manufacturing complexity increases and memory array reliability is compromised
Solution Approach 1:
The patent separates the coil formation to dedicated regions on separate chips rather than integrating it into the peripheral circuit region of the memory chip. This segmentation avoids the need for exclusive metal wiring in the memory chip's peripheral region, maintaining manufacturing simplicity and memory array reliability while still enabling wireless communication through the stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient installation of a large coil on the memory array, enabling long-distance communications and increased channel formation, while being tolerant of chip misalignment and reducing manufacturing costs by utilizing existing metal wiring layers.
Implementation Method 1
an antenna formed by a metal wiring layer being overlapped with a region where the memory array exists
Implementation Method 2
the first and second antennas carry out wireless communications with each other
Data Source
AI summary
An electronic circuit, for which a coil 22 is disposed being overlapped with a region of a memory array 11, carries out communications by inductive coupling between stacked and mounted chips by means of the coil 22. Because each side of the coil 22 is disposed so as not to be parallel to a word line and a bit line 15, crosstalk between ‘the coil 22’ and ‘the word line 14 and bit line 15’ can minimized. This allows efficiently arranging a coil to carry out communications by inductive coupling between chips to be stacked and mounted.