Inductive Coupling for 3D Memory Interconnects
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Solution Overview
Problem
In three-dimensional stack mounting of nonvolatile semiconductor memory devices, the complexity and cost of manufacturing processes for through-via formation and the increased chip area due to inductor element formation hinder efficient inter-chip communication, particularly when a large number of chips are stacked, leading to performance degradation and increased manufacturing costs.
Innovation Solution
A nonvolatile semiconductor memory device configuration utilizing a common inductor element for both transmission and receiving circuits, with a control chip having a larger inductor element than the memory chips, allowing for inter-chip communication through inductive coupling, reducing chip area and manufacturing complexity, and enabling high-speed interfaces without increasing the number of wire bondings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through-via is formed to penetrate the substrate for inter-chip communication, then signal transmission between chips is enabled, but manufacturing complexity and costs increase
Solution Approach 1:
The patent extracts the inductor element from the substrate structure and places it only on specific chips (transmitter or receiver) that require communication functionality. This eliminates the need for through-vias to penetrate all substrate layers, reducing manufacturing complexity while maintaining inter-chip communication capability through magnetic coupling between externally mounted inductors
2Reliability
If an inductor element is formed in the semiconductor chip for communication, then inter-chip signal transmission is achieved, but chip area increases
Solution Approach 1:
The patent moves the inductor element from the two-dimensional chip plane to the three-dimensional external space by mounting it on the chip surface or behind the chip. This dimensional transition allows the inductor to be positioned outside the main chip area, reducing the occupied chip area while maintaining the necessary inductance value for communication
3Reliability
If wire bonding is used for signal transmission between stacked chips, then inter-chip communication is achieved, but the number of wire bondings becomes excessive when many chips are stacked
Solution Approach 1:
The patent replaces the mechanical wire bonding system with an electromagnetic field-based communication system using inductors. Magnetic coupling between inductors on adjacent chips enables signal transmission without physical wire connections, dramatically reducing the number of wire bondings required while supporting multi-chip stacking configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances inter-chip communication efficiency, reduces power consumption, and prevents chip area expansion, enabling high-speed interfaces and simpler asynchronous communication systems, even with increased chip stacking, while maintaining manufacturing cost-effectiveness.
Implementation Method 1
inter-chip communication by inductive coupling between inductor elements
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors.