Inductively Peaked Delay Cell for Wide-Range Quadrature Clocks
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Solution Overview
Problem
The transition from 112 G-PAM4 to 224 G-PAM4 in serial IO systems poses challenges in achieving similar energy efficiency and jitter performance due to increased clocking power requirements and the need for variable delay in quadrature clock distribution, especially at high frequencies like 28 GHz.
Innovation Solution
A quadrature clock generator utilizing a shunt-series inductively peaked clock buffer with a resistor digital-to-analog converter (R-DAC) is employed, allowing for low-jitter clock generation across a wide frequency range with minimal additional stages, and a delay cell that provides a large delay tuning range suitable for high-frequency clocks, thereby reducing capacitive loading and enhancing jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock frequency is increased to 28 GHz for 224 G-PAM4 operation, then data rate is improved, but clocking power consumption increases by 8× or higher
Solution Approach 1:
The patent implements dynamic delay adjustment in the quadrature generator Q-path using a resistor DAC that can be tuned to provide variable delay (7.81 ps at 32 GHz to 15.62 ps at 16 GHz). This dynamic adaptation allows the system to maintain proper quadrature timing across different clock frequencies and data rates, enabling efficient operation at 28 GHz while managing power consumption through optimized timing rather than brute-force power increases
Solution Approach 2:
The patent changes the delay parameter in the Q-path by introducing a resistor DAC that provides continuous delay tuning capability. By adjusting the delay parameter dynamically based on operating conditions, the system achieves proper quadrature generation at high frequencies without requiring excessive clocking power, thus resolving the contradiction between data rate and power consumption
2Adaptability or versatility
If multiple PLLs are used to support multiple clock frequencies, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal quadrature generator design that can operate across multiple clock frequencies (16-32 GHz range) using a single configurable architecture. The resistor DAC provides continuous delay tuning that adapts the Q-path to different operating frequencies, eliminating the need for multiple dedicated PLL configurations and reducing overall system complexity while maintaining multi-frequency support
3Adaptability or versatility
If variable delay is added to Q-path for one-octave frequency operation, then adaptability is improved, but jitter performance deteriorates
Solution Approach 1:
The patent introduces a resistor DAC as an intermediary element in the Q-path that provides smooth, continuous delay adjustment rather than discrete steps. This intermediary component enables precise timing control that maintains jitter performance while adapting to different frequencies, as the continuous tuning capability avoids the timing discontinuities that would otherwise degrade jitter performance
Solution Approach 2:
The patent implements dynamic delay tuning in the Q-path using a resistor DAC that can be adjusted in real-time to match the required delay for each operating frequency. This dynamic adaptation ensures that the quadrature timing relationship is maintained with high precision across the full frequency range, preventing jitter degradation that would occur with static delay configurations
Data Source
AI summary
A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.