On-Chip Inductor Air-Gap Isolation for Lower Substrate Loss

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Solution Overview

Problem

The challenge in semiconductor device fabrication is to balance the size of on-chip inductors with their quality factor, as increasing the quality factor leads to increased energy losses and reduced space efficiency.

Innovation Solution

The integration of sealed cavities with air gaps in the semiconductor substrate beneath the inductor windings, which reduces energy losses by utilizing air gaps with low permittivity, thereby enhancing the quality factor without increasing the inductor's footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the inductor size is increased to reduce energy losses and improve quality factor, then the quality factor is improved, but the space occupied on the chip increases

Engineering Contradiction:
Improveenergy lossesVSAvoidinductor footprint
Core Design Contradiction:
Loss of energyVSArea of stationary object

Solution Approach 1:

The patent introduces sealed cavities with air gaps in the vertical dimension beneath the inductor windings. By utilizing the third dimension (depth below the chip surface) rather than expanding the inductor footprint in the horizontal plane, the design reduces energy losses to the substrate while maintaining a compact on-chip footprint. The air gaps are formed by etching cavities through the substrate and sealing them with dielectric layers, creating an electromagnetic isolation structure that extends vertically below the inductor.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces air gaps as an intermediary medium between the inductor windings and the semiconductor substrate. These air gaps, with their low permittivity, act as an electromagnetic isolation layer that reduces energy losses and parasitic capacitance. The air gaps are created by forming sealed cavities in the substrate and filling them with air or vacuum, thereby mediating the interaction between the inductor and substrate to improve the quality factor without increasing the inductor's physical size.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If sealed cavities with air gaps are introduced to reduce energy losses, then the quality factor is enhanced, but the device structure complexity increases

Engineering Contradiction:
Improveenergy lossesVSAvoidstructure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the semiconductor substrate into multiple sealed cavities, each containing an air gap. Rather than creating a single complex structure, the substrate is divided into discrete cavity regions that can be independently formed and sealed. This segmentation allows for modular fabrication using standard semiconductor processing techniques, reducing overall structural complexity while achieving the desired electromagnetic isolation effect across the entire inductor area.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach optimizes inductor performance by reducing energy losses to the substrate while maintaining a compact design, thus improving the quality factor without expanding the inductor's physical size.

Implementation Method 1

reduces energy losses by utilizing air gaps with low permittivity

Methodology Applied
Scientific EffectPermittivity: Dielectric Permittivity

Data Source

PatentEP4679462A1Inductors with airgap electrical isolation
Publication Date: 2026.01.14 GLOBALFOUNDRIES US INC
  • EP4679462A1 patent drawingFigure 1
  • EP4679462A1 patent drawingFigure 2
  • EP4679462A1 patent drawingFigure 2A

AI summary

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities.