On-Chip Inductor Branch Structure for Tunable Coupling
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Solution Overview
Problem
Conventional on-chip inductors face challenges in adjusting circuit parameters such as inductance and coupling due to the limited range of the branch structure, making it difficult to meet various circuit-design demands.
Innovation Solution
The semiconductor device features conductive lines disposed in insulating layers, overlapping and extending along winding portions to increase coupling and inductance, allowing for adjustable locations of extending portions and enhanced circuit design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the branch structure location is limited within the innermost coil area, then the inductor structure is compact, but the tuning range for inductance and coupling parameters is restricted
Solution Approach 1:
The patent extends the branch structure from the traditional planar configuration within the innermost coil to a three-dimensional configuration that overlaps with conductive lines in different insulating layers. This vertical dimensionality change allows the branch structure to extend beyond the innermost coil area while maintaining compactness, thereby expanding the tuning range for inductance and coupling parameters without significantly increasing device complexity.
Solution Approach 2:
The patent implements a nested structure where the branch structure in the second insulating layer overlaps with and is integrated around conductive lines in the first insulating layer. This nesting approach allows multiple functional elements to occupy overlapping spatial regions, maximizing the use of available space and enabling extended tuning capabilities without proportionally increasing the overall device footprint or complexity.
2Adaptability or versatility
If the first inductance value, second inductance value and coupling parameter are adjusted by changing the connecting location, then the circuit parameters can be tuned, but the adjustment range is limited by the innermost coil side length
Solution Approach 1:
The patent transitions from two-dimensional parameter adjustment within the plane of the innermost coil to three-dimensional adjustment by overlapping conductive lines across multiple insulating layers. This allows the branch structure to connect at multiple vertical positions, effectively extending the adjustment range for circuit parameters beyond the physical constraints of the innermost coil side length while maintaining compact device dimensions.
3Reliability
If conductive lines overlap and extend along winding portions, then coupling and inductance are increased, but the device occupies more vertical space
Solution Approach 1:
The patent nests conductive lines from different insulating layers in overlapping vertical positions, allowing them to occupy the same horizontal footprint while at different vertical levels. This nesting configuration increases coupling and inductance through enhanced magnetic field interaction between overlapping conductors, while the vertical stacking efficiently utilizes three-dimensional space without proportionally increasing the overall device volume.
Data Source
AI summary
A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.