Inductor Chip With Trapezoidal Coil Patterns

The patent transitions from increasing coil width (horizontal dimension) to increasing coil thickness (vertical dimension) to reduce resistance. By forming multiple stacked coil patterns in the thickness direction, the effective cross-sectional area for current flow increases without expanding the planar width, thus reducing DC resistance while maintaining adequate spacing between patterns to prevent short circuits.

The patent implements nested coil structures where multiple coil patterns are stacked vertically, with each coil pattern serving as a turn in the inductor. The coil patterns are arranged in layers, with upper coils positioned above lower coils in the thickness direction, creating a compact nested configuration that increases the number of turns within a limited space while maintaining electrical isolation between layers.

The patent segments the coil pattern formation into multiple discrete plating steps, each forming a portion of the total coil thickness. Instead of attempting to form the entire thick coil pattern in a single plating step requiring a bulky plating resist, the process divides the formation into sequential steps, allowing each plating resist to be thinner and more easily formed while achieving the desired high aspect ratio through cumulative thickness buildup.

The patent employs preliminary actions by forming intermediate coil patterns and their corresponding plating resists in sequential steps before completing the final coil structure. Each plating resist is formed with a width sufficient to maintain its shape during its specific plating step, and subsequent resists are formed on top of previously plated coils, allowing each individual resist to be structurally sound without requiring excessive width.

The patent applies preliminary protective actions by forming insulation layers between stacked coil patterns before subsequent plating steps. The insulation layer is deposited on the surface of previously formed coils, creating a protective barrier that prevents the isotropic growth of subsequent coil patterns from causing short circuits. This preliminary insulation step allows electroplating to proceed while maintaining electrical isolation between adjacent coils in the stack.

The patent applies different properties to different regions of the coil structure by using insulation layers selectively between coil patterns. The coil patterns themselves maintain their conductive properties for electrical function, while the regions between them are locally modified with insulating material to prevent short circuits. This local differentiation of properties allows simultaneous achievement of electrical connectivity within coils and electrical isolation between coils.