Inductor Driver Integrator Circuit for Fast High-Current Ramps
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Solution Overview
Problem
Conventional integrator circuits using operational amplifiers are unable to produce the peak current requirements with sufficient linearity and speed necessary for driving small inductive coils.
Innovation Solution
An integrator circuit design utilizing three transistors and an integrator capacitor, which integrates a linear current ramp to develop high peak currents through an inductive load in a short time, achieving good linearity by compensating for drain current dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional operational amplifier is used in the integrator circuit, then the circuit provides signal conditioning functions, but it cannot produce the peak current requirements with sufficient linearity and speed necessary for driving a small inductive coil
Solution Approach 1:
The operational amplifier is segmented into three separate transistors (first transistor, second transistor, third transistor) arranged in a cascaded configuration. This segmentation allows each transistor to perform a specific function: the first transistor processes the input current ramp, the second transistor integrates the current while maintaining linearity through constant current biasing, and the third transistor delivers the high peak current to the inductive load. This division resolves the contradiction by enabling both high speed and good linearity simultaneously.
Solution Approach 2:
The circuit changes the operating parameters by using a constant current source to bias the second transistor, which maintains a stable integration current regardless of voltage variations. This parameter control ensures that the integration process maintains high linearity while the cascaded transistor structure enables fast response. The gate voltages are also dynamically adjusted to optimize both speed and linearity performance.
2Power
If a conventional operational amplifier is used in the integrator circuit, then the circuit provides desired current response, but it cannot deliver high peak currents with sufficient speed
Solution Approach 1:
The operational amplifier is segmented into three separate transistors (first transistor, second transistor, third transistor) arranged in a cascaded configuration. This segmentation allows each transistor to perform a specific function: the first transistor processes the input current ramp, the second transistor integrates the current while maintaining linearity through constant current biasing, and the third transistor delivers the high peak current to the inductive load. This division resolves the contradiction by enabling both high speed and good linearity simultaneously.
Solution Approach 2:
The circuit employs periodic switching of the third transistor to deliver high peak currents in controlled pulses to the inductive load. The gate of the third transistor is switched periodically to allow rapid current buildup during the integration phase, achieving both high power delivery and fast response. This periodic action enables the circuit to meet the peak current requirements while maintaining high integration speed.
Data Source
AI summary
An apparatus includes a first transistor including a first gate, a first drain and a first source. A second transistor includes a second gate and a second source, the second gate is coupled to a first current source configured to generate a linear current ramp, the second source is coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor includes a third gate and a third source, the third gate is coupled to the first drain, and the third source is coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate.